
基本信息:
- 专利标题: METHOD OF ALIGNMENT MARK PROTECTION AND SEMICONDUCTOR DEVICE FORMED THEREBY
- 专利标题(中):对准标记保护和形成的半导体器件的方法
- 申请号:US12814228 申请日:2010-06-11
- 公开(公告)号:US20110304006A1 公开(公告)日:2011-12-15
- 发明人: Chiao-Wen Yeh , Chih-Hao Huang
- 申请人: Chiao-Wen Yeh , Chih-Hao Huang
- 专利权人: Macronix International Co., Ltd.
- 当前专利权人: Macronix International Co., Ltd.
- 主分类号: H01L23/544
- IPC分类号: H01L23/544 ; H01L21/71
摘要:
A method of protecting alignment marks from damage in a planarization process includes providing a substrate including a surface, forming trenches in the substrate from the surface, forming a first dielectric layer on the substrate, forming a second dielectric layer on the first dielectric layer, forming a patterned second dielectric layer by removing second dielectric over the trenches, resulting in openings defined by the trenches and the patterned second dielectric layer, forming a third dielectric layer on the patterned second dielectric layer, the third dielectric layer filling the openings, and planarizing the third dielectric layer by using the patterned second dielectric layer as a stop layer, resulting in residual third dielectric in the openings that includes a first portion in the substrate and a second portion above the surface of the substrate.
摘要(中):
在平坦化工艺中保护对准标记免受损伤的方法包括提供包括表面的衬底,从表面在衬底中形成沟槽,在衬底上形成第一介电层,在第一介电层上形成第二介电层,形成 图案化的第二介电层,通过在沟槽上去除第二电介质,导致由沟槽和图案化的第二介电层限定的开口,在图案化的第二介电层上形成第三电介质层,填充开口的第三电介质层, 通过使用图案化的第二介电层作为阻挡层,在开口中产生残留的第三电介质,其包括衬底中的第一部分和衬底表面上的第二部分。
公开/授权文献:
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L23/00 | 半导体或其他固态器件的零部件 |
--------H01L23/544 | .加到半导体器件上的标志,例如注册商标、测试图案 |