基本信息:
- 专利标题: 用於製造用以形成三維單片積體電路之結構的方法
- 专利标题(英):Method for manufacturing a structure for forming a tridimensional monolithic integrated circuit
- 专利标题(中):用于制造用以形成三维单片集成电路之结构的方法
- 申请号:TW106111032 申请日:2017-03-31
- 公开(公告)号:TW201802881A 公开(公告)日:2018-01-16
- 发明人: 菲古特 克里斯多夫 , FIGUET, CHRISTOPHE , 艾卡諾特 路多維克 , ECARNOT, LUDOVIC , 阮 碧煙 , NGUYEN, BICH-YEN , 史瓦然貝區 瓦特 , SCHWARZENBACH, WALTER , 戴爾普瑞特 丹尼爾 , DELPART, DANIEL , 拉杜 優娜特 , RADU, IONUT
- 申请人: 索泰克公司 , SOITEC
- 专利权人: 索泰克公司,SOITEC
- 当前专利权人: 索泰克公司,SOITEC
- 代理人: 惲軼群; 劉法正
- 优先权: 1652768 20160331
- 主分类号: H01L21/18
- IPC分类号: H01L21/18 ; H01L21/306 ; H01L25/00
The invention relates to a method for manufacturing a structure comprising a first substrate (1) comprising at least one electronic component (10) likely to be damaged by a temperature higher than 400 DEG C and a semi-conductor layer extending on said first substrate, characterised in that it comprises the following steps of: (a) providing a first bonding metal layer (11) on the first substrate (1), (b) providing a second substrate (2) comprising successively: - a semi-conductor base substrate (20), - a stack (21) of a plurality of semi-conductor epitaxial layers, a layer (210) of SixGe1-x, with 0 ≤ x ≤ 1 being located at the surface of said stack (21) opposite to the base substrate (20), - a second bonding metal layer (22), (c) bonding the first substrate and the second substrate through the first and second bonding metal layers (11, 22), said bonding step being carried out at a temperature lower than or equal to 400 DEG C, (d) removing a part of the second substrate so as to transfer the layer (210) of SixGe1-x on the first substrate (1), said removing comprising at least selectively chemically etching a layer of the second substrate (2) relative to the SixGe1-x layer (210).
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L21/00 | 专门适用于制造或处理半导体或固体器件或其部件的方法或设备 |
--------H01L21/02 | .半导体器件或其部件的制造或处理 |
----------H01L21/027 | ..未在H01L21/18或H01L21/34组中包含的为进一步的光刻工艺在半导体之上制作掩膜 |
------------H01L21/18 | ...器件有由周期表第Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体,如掺杂材料 |