基本信息:
- 专利标题： 薄型晶片堆疊封裝構造及其製造方法
- 专利标题（英）：Thin stacked chip package and the method for manufacturing the same
- 专利标题（中）：薄型芯片堆栈封装构造及其制造方法
- 申请号：TW105137133 申请日：2016-11-14
- 公开(公告)号：TW201737442A 公开(公告)日：2017-10-16
- 发明人： 林俊德 , LIN, CHUN TE , 林基正 , LIN, JI CHENG , 朱哲民 , CHU, CHE MIN , 黄建文 , HUANG, CHIEN WEN , 方立志 , FANG, LI CHIH
- 申请人： 力成科技股份有限公司 , POWERTECH TECHNOLOGY INC.
- 申请人地址： 新竹縣
- 专利权人： 力成科技股份有限公司,POWERTECH TECHNOLOGY INC.
- 当前专利权人： 力成科技股份有限公司,POWERTECH TECHNOLOGY INC.
- 当前专利权人地址： 新竹縣
- 代理人： 葉璟宗; 詹東穎; 劉亞君
- 优先权： 62/316,843 20160401
- 主分类号： H01L23/485
- IPC分类号： H01L23/485 ; H01L23/488 ; H01L23/16 ; H01L21/60
Disclosed is a thin stacked chip package. A plurality of electrodes are disposed on an active surface of the chip. A plurality of via-stopping components including stud bumps are formed the corresponding electrodes. A molding compound encapsulates the chip. A plurality of through holes are formed on the molding. A conductive material is deposited in each of the through holes to form Cu post between a top surface of the molding and the corresponding via-stopping components. A redistribution layer (RDL) is formed on the top surface of the molding compound. Conductive materials disposed within the RDL may form a plurality of circuits coupled to the metal post to form electrical connection with the chip. A passivation layer is formed to cover the RDL. In this way, the package thickness may be reduced. Thus, the chip damage caused by the formation of through holes in the mold is reduced and there is only a need for one-time molding of the chip.
公开/授权文献:
- TWI606563B 薄型晶片堆疊封裝構造及其製造方法 公开/授权日：2017-11-21
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L23/00 | 半导体或其他固态器件的零部件 |
| --------H01L23/34 | .冷却装置；加热装置；通风装置或温度补偿装置 |
| ----------H01L23/482 | ..由不可拆卸地施加到半导体本体上的内引线组成的 |
| ------------H01L23/485 | ...包括导电层和绝缘层组成的层状结构，例如平面型触头 |