基本信息:
- 专利标题： 半導體裝置及其製造方法
- 专利标题（英）：Semiconductor device, and production method therefor
- 专利标题（中）：半导体设备及其制造方法
- 申请号：TW104133915 申请日：2015-10-15
- 公开(公告)号：TW201622105A 公开(公告)日：2016-06-16
- 发明人： 谷口泰弘 , TANIGUCHI, YASUHIRO , 川嶋泰彥 , KAWASHIMA, YASUHIKO , 葛西秀男 , KASAI, HIDEO , 櫻井良多郎 , SAKURAI, RYOTARO , 品川裕 , SHINAGAWA, YUTAKA , 奧山幸祐 , OKUYAMA, KOSUKE
- 申请人： 芙洛提亞股份有限公司 , FLOADIA CORPORATION
- 专利权人： 芙洛提亞股份有限公司,FLOADIA CORPORATION
- 当前专利权人： 芙洛提亞股份有限公司,FLOADIA CORPORATION
- 代理人： 陳長文
- 优先权： 2014-211098 20141015;PCT/JP2015/078336 20151006
- 主分类号： H01L27/06
- IPC分类号： H01L27/06 ; H01L21/8239
Provided is a semiconductor device (1) in which a contact (C5a) is provided so as to extend to a first selection gate electrode (G2a) from the top of a contact installation structure (10a) having the same configuration as a memory gate structure (4a). Accordingly, a conventional mounting section (102b) mounting the top of the memory gate structure (110) is not formed (fig. 13), and thus the distance to an upper-layer wiring layer can be shortened, the aspect ratio can be reduced, and, as a result, an increase in the contact resistance value can be inhibited. Furthermore, the conventional mounting section (102b) mounting the top of the memory gate structure (110) is not formed, and thus the contact installation structure (10a) and the upper-layer wiring layer can be kept apart, and, as a result, contact failure with the upper-layer wiring layer can be inhibited. Also provided is a production method for said semiconductor device.
公开/授权文献:
- TWI610418B 半導體裝置及其製造方法 公开/授权日：2018-01-01
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L27/00 | 由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件 |
| --------H01L27/02 | .包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的；包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的 |
| ----------H01L27/04 | ..其衬底为半导体的 |
| ------------H01L27/06 | ...在非重复结构中包括有多个单个组件的 |