PURPOSE: A gate driving circuit and a display device including the same are provided to reduce a delay section and to improve a high level of a gate signal by increasing a channel length of at least one transistor connected to a Q node to increase a signal level of the Q node in a boost-up section. CONSTITUTION: A gate output unit includes a plurality of stages. An n-th stage includes a clock terminal, a first input terminal, a second input terminal, a third input terminal, a first voltage terminal, a second voltage terminal, a first output terminal, and a second output terminal. A gate output unit(230) outputs a plurality of gate signals. The n-th stage includes a first transistor. The first transistor outputs a high voltage of a clock signal to a high voltage of the n-th gate signal. A first node control unit controls a signal of a control node and includes at least one transistor with a longer channel length than the channel length of the first transistor. A carry unit(240) outputs the high voltage of the clock signal to an n-th carry signal. A buffer unit(210) includes a fourth transistor. The fourth transistor applies the high voltage of the carry signal to the control node.