基本信息:
- 专利标题: 주파수 분할기 및 주파수 분할기 회로를 구현하기 위한 방법 및 프로세서-판독가능한 매체
- 专利标题(英):High speed divide-by-two circuit
- 专利标题(中):高速双向电路
- 申请号:KR1020127002990 申请日:2010-07-02
- 公开(公告)号:KR1020120047928A 公开(公告)日:2012-05-14
- 发明人: 찬,니가르,룽,아란 , 왕,센
- 申请人: 퀄컴 인코포레이티드
- 申请人地址: **** Morehouse Drive, San Diego, CA *****-****, U.S.A.
- 专利权人: 퀄컴 인코포레이티드
- 当前专利权人: 퀄컴 인코포레이티드
- 当前专利权人地址: **** Morehouse Drive, San Diego, CA *****-****, U.S.A.
- 代理人: 특허법인 남앤드남
- 优先权: US12/496,875 2009-07-02
- 国际申请: PCT/US2010/040979 2010-07-02
- 国际公布: WO2011003101 2011-01-06
- 主分类号: H03K3/356
- IPC分类号: H03K3/356
The high frequency divider comprises a plurality of differential latches. And a coupled P- channel transistors and the variable resistive elements, wherein each latch comprises a pair of crossed. The latch is supplied to the multi-variable resistance element - is controlled so as to have a lower output resistance value at high frequency operation by setting the control bit digital value. For controlling the latches so as to have a reduced output resistance value at high frequency is to be maintained for the 3dB bandwidth is wide operating frequency range of the latch. The variable resistance element is disposed between the large DC bias currents have two differential output nodes of the latch does not flow through the variable resistance element. As a result, the output signal remains in a good high frequency voltage swing, the divider current consumption is reduced compared to the increased output signal swing and the current consumption in the conventional differential latch divider, it does not increase significantly at higher frequencies.
公开/授权文献:
- KR101418033B1 주파수 분할기 및 주파수 분할기 회로를 구현하기 위한 방법 및 프로세서-판독가능한 매체 公开/授权日:2014-07-09