基本信息:
- 专利标题： 레벨 시프트 회로, 반도체 장치
- 专利标题（英）：KR101931408B1 - Level shift circuit, semiconductor device
- 申请号：KR1020157000563 申请日：2012-08-01
- 公开(公告)号：KR101931408B1 公开(公告)日：2018-12-20
- 发明人： 가와사끼,요이찌
- 申请人： 르네사스 일렉트로닉스 가부시키가이샤
- 申请人地址： *-**, Toyosu *-chome, Koutou-ku, Tokyo, Japan
- 专利权人： 르네사스 일렉트로닉스 가부시키가이샤
- 当前专利权人： 르네사스 일렉트로닉스 가부시키가이샤
- 当前专利权人地址： *-**, Toyosu *-chome, Koutou-ku, Tokyo, Japan
- 代理人： 장수길; 이중희
- 国际申请： PCT/JP2012/069593 2012-08-01
- 国际公布： WO2014020724 2014-02-06
- 主分类号： H03K19/0185
- IPC分类号： H03K19/0185 ; H03K3/356
The level shift circuit comprises a first (Q5, Q7) and the second latch circuit including an inverter circuit of the (Q6, Q8) (Q5, Q6, Q7, Q8) and, MOS for a first type of operation by the input signal and a transistor (Q1), and a 2 second MOS transistor (Q2) and a current-to-voltage control MOS transistor (Q9) for input of operation by the inverted signal of the input signal. A latch circuit (Q5, Q6, Q7, Q8), and outputs the voltage obtained by converting the level of the input voltage. The first and second type MOS transistors (Q1, Q2) by an input signal received by the gate terminal, and drives the latch circuit (Q5, Q6, Q7, Q8), depending on the input signal. As a current-to-voltage control MOS transistor (Q9) is provided between the MOS transistor for the input (Q1, Q2) and a latch circuit (Q5, Q6, Q7, Q8), receiving the input of the control voltage at a gate terminal, inverting the latch circuit It is driven according to the operation.
公开/授权文献:
- KR1020150040268A 레벨 시프트 회로, 반도체 장치 公开/授权日：2015-04-14
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H03 | 基本电子电路 |
| ----H03K | 脉冲技术 |
| ------H03K19/00 | 逻辑电路，即，至少有两个输入作用于一个输出的；倒向电路 |
| --------H03K19/01 | .提高开关速度的改进 |
| ----------H03K19/0185 | ..仅使用场效应晶体管的 |