基本信息:
- 专利标题： 래치 회로 및 표시장치
- 专利标题（英）：Latch circuit and display device using the latch circuit
- 专利标题（中）：锁存电路和显示装置使用锁存电路
- 申请号：KR1020120115125 申请日：2012-10-17
- 公开(公告)号：KR101489744B1 公开(公告)日：2015-02-04
- 发明人： 미야자와,토시오 , 아키모토,하지메
- 申请人： 픽스트로닉스 인코포레이티드
- 申请人地址： **** Morehouse Drive, San Diego, California *****-****, U.S.A.
- 专利权人： 픽스트로닉스 인코포레이티드
- 当前专利权人： 픽스트로닉스 인코포레이티드
- 当前专利权人地址： **** Morehouse Drive, San Diego, California *****-****, U.S.A.
- 代理人： 특허법인 남앤드남
- 优先权： JPJP-P-2011-227851 2011-10-17
- 主分类号： H03K3/356
- IPC分类号： H03K3/356 ; G09G3/20
Suppressing the drain Oh Balan body effect, and provides a latch circuit capable of improving the reliability. When the said scanning voltage input to the gate, a "0" or the input transistor to blow a voltage corresponding to the data of "1", at the same time that the capacity control signal input to the other end, one end to the second electrode of the input transistor is connected, a holding capacitor which holds a voltage blown to the input transistor, while the gate is connected to the second electrode of the input transistor, a second electrode is connected to the first output terminal, the first latch on the first electrode at the same time that the first transistor of the first conductivity type to which a control signal is input, and the gate is connected to the second electrode of the first transistor, a second electrode is connected to the second output terminal, the second latch control to the first electrode and a second transistor of a second conductivity type in which a signal is input.
公开/授权文献:
- KR1020130041751A 래치 회로 및 표시장치 公开/授权日：2013-04-25