基本信息:
- 专利标题： 적응적 클록 생성기들, 시스템들 및 방법들
- 专利标题（英）：Adaptive clock generators, systems, and methods
- 专利标题（中）：自适应时钟发生器，系统和方法
- 申请号：KR1020127018583 申请日：2010-12-14
- 公开(公告)号：KR101459533B1 公开(公告)日：2014-11-10
- 发明人： 가그,매니쉬 , 차이,치아밍 , 브리지스,제프리토드
- 申请人： 퀄컴 인코포레이티드
- 申请人地址： **** Morehouse Drive, San Diego, CA *****-****, U.S.A.
- 专利权人： 퀄컴 인코포레이티드
- 当前专利权人： 퀄컴 인코포레이티드
- 当前专利权人地址： **** Morehouse Drive, San Diego, CA *****-****, U.S.A.
- 代理人： 특허법인 남앤드남
- 优先权： US12/637,321 2009-12-14
- 国际申请： PCT/US2010/060361 2010-12-14
- 国际公布： WO2011081951 2011-07-07
- 主分类号： H03K3/03
- IPC分类号： H03K3/03 ; H03K5/00
The reduced performance margin or be adaptive clock generator used to generate the clock signals for the functional circuit in order to avoid, systems and associated methods are disclosed. In certain embodiments, the clock generator generates a clock signal as its own and adaptively depending on the delay path (s) supplied to the delay circuit (s) for the selected delay path (s) of the functional circuit (s). The clock generator includes a functional circuit (s) of the delay circuit is adapted to delay the input signal by an amount related to a delay path (s) (s) to generate a receive input signal and output signal. The feedback circuit is responsive to the output signal being coupled to the delay circuit (s), wherein the feedback circuit is adapted to generate a re-input to the delay circuit (s) in the oscillation loop configuration. Input signal may be used to provide a clock signal to the functional block (s).
公开/授权文献:
- KR1020120112576A 적응적 클록 생성기들, 시스템들 및 방법들 公开/授权日：2012-10-11