基本信息:
- 专利标题： 컨텐츠－어드레서블 메모리에서의 어드레스 비교의 합산을 위한 방법들 및 장치
- 专利标题（英）：Methods and apparatus for sum of address compare in a content-addressable memory
- 专利标题（中）：一种内容可寻址存储器中地址比较的方法和装置
- 申请号：KR1020127027012 申请日：2011-03-18
- 公开(公告)号：KR101388168B1 公开(公告)日：2014-04-22
- 发明人： 오지멕,티모시에드워드
- 申请人： 퀄컴 인코포레이티드
- 申请人地址： **** Morehouse Drive, San Diego, CA *****-****, U.S.A.
- 专利权人： 퀄컴 인코포레이티드
- 当前专利权人： 퀄컴 인코포레이티드
- 当前专利权人地址： **** Morehouse Drive, San Diego, CA *****-****, U.S.A.
- 代理人： 특허법인 남앤드남
- 优先权： US12/727,623 2010-03-19
- 国际申请： PCT/US2011/029052 2011-03-18
- 国际公布： WO2011116322 2011-09-22
- 主分类号： G11C15/00
- IPC分类号： G11C15/00 ; G06F7/02
For example, the translation lookaside buffer and content addressable technology for adding the address comparison (A + B = K) for use in operation block memory device are described. The address input signals A and B are supplied as inputs to the A + B = K K is calculated the previous value stored in the plurality of memory cells. In each memory cell, the single logic gate circuit output and its version is generated in response to the updating of memory cells, each of the single logic gate circuit has as an input the associated memory cell outputs, and then the least significant bit adjacent to the memory cell output. In memory cells, respectively, some of the memory cells associated with A + B = K operation is generated at a portion a look-up comparison circuit, the corresponding address input signals A and B during a read look-up comparison operation, the associated memory cell outputs, and generating the single output logic gate circuit and is combined with his version.
公开/授权文献:
- KR1020130005292A 컨텐츠－어드레서블 메모리에서의 어드레스 비교의 합산을 위한 방법들 및 장치 公开/授权日：2013-01-15