基本信息:
- 专利标题: 반도체소자 탑재용 패키지 기판과 그 제조방법
- 专利标题(英):Package substrate for mounting semiconductor element and method for manufacturing the package substrate
- 专利标题(中):用于安装半导体元件的封装基板和用于制造封装基板的方法
- 申请号:KR1020107024798 申请日:2009-09-29
- 公开(公告)号:KR101143042B1 公开(公告)日:2012-05-08
- 发明人: 타무라타다시 , 스기바야시마나부 , 스즈키쿠니지 , 핫토리키요오
- 申请人: 히타치가세이가부시끼가이샤
- 申请人地址: *-*, Marunouchi *-chome, Chiyoda-ku, Tokyo, ***-****, Japan
- 专利权人: 히타치가세이가부시끼가이샤
- 当前专利权人: 히타치가세이가부시끼가이샤
- 当前专利权人地址: *-*, Marunouchi *-chome, Chiyoda-ku, Tokyo, ***-****, Japan
- 代理人: 특허법인원전
- 优先权: JPJP-P-2008-250302 2008-09-29; JPJP-P-2009-222738 2009-09-28
- 国际申请: PCT/JP2009/066918 2009-09-29
- 国际公布: WO2010035866 2010-04-01
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H05K3/46 ; H01L23/12
The present invention, in the case of constituting the PoP, the degree of freedom of combining packages large, small, even constraints pattern design, it is possible semiconductor device package mounting board for performing a connection between the upper package and the lower package, at a high density and a process for producing to provide a method for the purpose. The present invention, the cavity material and the adhesive comprises and, with them a cavity layer extending through and, by means of the adhesive and the laminated base layer to the cavity layer, which is formed by the open cavity portion, the floor formed by the through-hole to a semiconductor device package mounting board having a via which, being the inner layer circuit installed in the cavity layer, the inner layer circuit and to bond metallic coating on the inner wall of the via with the ground is formed by plating, the ground a via and a method for manufacturing a package substrate for mounting a semiconductor element to be conductive resin is filled in with.
公开/授权文献:
- KR1020100130640A 반도체소자 탑재용 패키지 기판과 그 제조방법 公开/授权日:2010-12-13
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L23/00 | 半导体或其他固态器件的零部件 |
--------H01L23/48 | .用于向或自处于工作中的固态物体通电的装置,例如引线、接线端装置 |