A while reducing cell size, placing the distance between adjacent storage elements at regular intervals.
A semiconductor memory device of one embodiment, the substrate and, provided on the first layer above the substrate, extending along a first direction, the first wiring adjacent along the second direction and the second a wiring provided on the second layer above the first layer, extending along a second direction, the third wiring and the fourth wiring adjacent along the first direction, provided on the upper surface of the first wiring comprising a first and a second memory cell that is, a third memory cell provided on the upper surface of the second wiring, the. Each of the first to third memory cell includes a variable resistance element and a selector. The selector of the first memory cell includes a gate coupled to the third wiring. Each of the selectors of the selectors and the third memory cell of the second memory cell includes a gate coupled to the fourth wiring. The variable resistance element of the first to third memory cell is located at equal distances from one another along the first surface.
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