基本信息:
- 专利标题: Stacked chip package and method of manufacturing the same
- 专利标题(中):堆叠芯片包装及其制造方法
- 申请号:JP2011106804 申请日:2011-05-12
- 公开(公告)号:JP2012084841A 公开(公告)日:2012-04-26
- 发明人: SASAKI YOSHITAKA , ITO HIROYUKI , IKEJIMA HIROSHI , IIJIMA ATSUSHI
- 申请人: Headway Technologies Inc , Sae Magnetics(H.K.)Ltd , ヘッドウェイテクノロジーズ インコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
- 专利权人: Headway Technologies Inc,Sae Magnetics(H.K.)Ltd,ヘッドウェイテクノロジーズ インコーポレイテッド,新科實業有限公司SAE Magnetics(H.K.)Ltd.
- 当前专利权人: Headway Technologies Inc,Sae Magnetics(H.K.)Ltd,ヘッドウェイテクノロジーズ インコーポレイテッド,新科實業有限公司SAE Magnetics(H.K.)Ltd.
- 优先权: US90260010 2010-10-12
- 主分类号: H01L25/065
- IPC分类号: H01L25/065 ; H01L25/07 ; H01L25/18 ; H01L27/10
摘要:
PROBLEM TO BE SOLVED: To enable stacking a plurality of stacked chip packages and electrically connecting them to each other by a simple structure, thereby providing a package including the desired number of semiconductor chips at a low cost.SOLUTION: A stacked chip package 1S comprises a main body 2. The main body 2 includes a main portion 2M, and a plurality of first terminals 4 and second terminals 5 disposed on the top surface and the bottom surface of the main portion 2M. The main portion 2M includes two layered portions 10S1 and 10S2, and a plurality of through electrodes T penetrating through the layered portions. The plurality of through electrodes T are electrically connected to the plurality of terminals 4 and 5. Each of the layered portions includes a semiconductor chip having a first surface and a second surface, and a plurality of surface electrodes. The layered portions 10S1 and 10S2 are bonded such that their second surfaces are facing each other. The terminals 4 are constituted using the surface electrodes of the layered portion 10S1, whereas the terminals 5 are constituted using the surface electrodes of the layered portion 10S2.
摘要(中):
要解决的问题:为了能够堆叠多个堆叠的芯片封装并且通过简单的结构将它们彼此电连接,从而以低成本提供包括期望数量的半导体芯片的封装。 解决方案:堆叠式芯片封装1S包括主体2.主体2包括主体部分2M,以及设置在主体部分的顶表面和底表面上的多个第一端子4和第二端子5 2M。 主体部分2M包括两个分层部分10S1和10S2,以及穿过分层部分的多个贯通电极T. 多个贯通电极T电连接到多个端子4和5.每个层叠部分包括具有第一表面和第二表面的半导体芯片和多个表面电极。 层叠部分10S1和10S2结合成使得它们的第二表面彼此相对。 端子4使用层叠部10S1的表面电极构成,端子5由层叠部10S2的表面电极构成。 版权所有(C)2012,JPO&INPIT
公开/授权文献:
- JP5313292B2 Stacked chip package and method of manufacturing the same 公开/授权日:2013-10-09
信息查询:
EspacenetIPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L25/00 | 由多个单个半导体或其他固态器件组成的组装件 |
--------H01L25/03 | .所有包含在H01L27/00至H01L51/00各组中同一小组内的相同类型的器件,例如整流二极管的组装件 |
----------H01L25/04 | ..不具有单独容器的器件 |
------------H01L25/065 | ...包含在H01L27/00组类型的器件 |