基本信息:
- 专利标题： Al base alloy wiring forming method of semiconductor device
- 专利标题（中）：AL基线合金形成半导体器件的方法
- 申请号：JP2004159627 申请日：2004-05-28
- 公开(公告)号：JP2005340640A 公开(公告)日：2005-12-08
- 发明人： ONISHI TAKASHI , YASUNAGA TATSUYA , FUJII HIDEO , YOSHIKAWA TETSUYA , MUNEMASA ATSUSHI
- 申请人： Kobe Steel Ltd , 株式会社神戸製鋼所
- 专利权人： Kobe Steel Ltd,株式会社神戸製鋼所
- 当前专利权人： Kobe Steel Ltd,株式会社神戸製鋼所
- 优先权： JP2004159627 2004-05-28
- 主分类号： H01L21/285
- IPC分类号： H01L21/285 ; H01L21/28 ; H01L21/3205 ; H01L23/52
摘要：
PROBLEM TO BE SOLVED: To provide a method for forming wiring for a reliable semiconductor device which stably exhibits high quality such as low electric resistance and excellent denseness and adhesion to an insulating film.
SOLUTION: Wiring of a semiconductor device is formed by forming a thin film 5 of Al or Al alloy (hereinafter, Al base metal) by sputtering on the surface of an insulating film 2 comprising a recess 3 formed on a substrate, and then applying high-temperature and high-pressure process so that the Al base metal is packed in the recess. The above sputtering is performed under conditions of 0.5-1.1 mTorr sputtering gas pressure, 3-15 W/cm
2 discharge power density, and 100-300°C substrate temperature.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要（中）：
SOLUTION: Wiring of a semiconductor device is formed by forming a thin film 5 of Al or Al alloy (hereinafter, Al base metal) by sputtering on the surface of an insulating film 2 comprising a recess 3 formed on a substrate, and then applying high-temperature and high-pressure process so that the Al base metal is packed in the recess. The above sputtering is performed under conditions of 0.5-1.1 mTorr sputtering gas pressure, 3-15 W/cm
2 discharge power density, and 100-300°C substrate temperature.
COPYRIGHT: (C)2006,JPO&NCIPI
要解决的问题：提供一种用于形成可靠的半导体器件的布线的方法，其稳定地表现出诸如低电阻和优异的致密性和对绝缘膜的粘附性的高质量。 解决方案：通过在包括形成在基板上的凹部3的绝缘膜2的表面上通过溅射形成Al或Al合金（以下称为Al贱金属）的薄膜5来形成半导体器件的布线，以及 然后施加高温和高压处理，使得Al贱金属包装在凹部中。 上述溅射在0.5-1.1mTorr溅射气体压力，3-15W / cm 2 SP / 2放电功率密度和100-300℃基板温度的条件下进行。 版权所有（C）2006，JPO＆NCIPI
公开/授权文献:
信息查询:
EspacenetIPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L21/00 | 专门适用于制造或处理半导体或固体器件或其部件的方法或设备 |
| --------H01L21/02 | .半导体器件或其部件的制造或处理 |
| ----------H01L21/027 | ..未在H01L21/18或H01L21/34组中包含的为进一步的光刻工艺在半导体之上制作掩膜 |
| ------------H01L21/18 | ...器件有由周期表第Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料 |
| --------------H01L21/26 | ....用波或粒子辐射轰击的 |
| ----------------H01L21/283 | .....用于电极的导电材料或绝缘材料的沉积 |
| ------------------H01L21/285 | ......气体或蒸气的沉积，例如冷凝 |