A multiloop PLL circuit comprising :
- a first PLL loop comprising a first VCO, a first phase detector having a first input receiving a reference frequency (Fref) and a second input receiving the output of a first programmable divider, which input receives the signal generated by the first VCO and a first loop filter connected between said first phase detector and said first VCO;
- at least one auxiliary PLL loop comprising a second VCO, a second phase detector, a second (R1) and a third (N1) programmable dividers , and a second loop filter
- a main loop for generating a desired output frequency Fout comprising a third VCO, a third phase detector, a fourth (Rn) and a fifth (Nn) programmable divider, a main loop filter and a mixer
additional possible auxiliary PLL loop each comprising a forth VCO, a forth phase detector, a sixth (Ri) and a seventh (Ni) programmable divider, a third auxiliary loop filter and a mixer
whereby the desired output frequency Fout is generated in accordance with the relation: F out = N 1 / R 1 + … + Nn / Rn * F cro Where
N1 and R1 are the dividing values of the first auxiliary loop and Ni and Ri with i=2 ... n-1 being the dividing ratios of any possible further auxiliary loop;
Fcro is the frequency generated by VCO.
Wherein said multiloop circuit is configured with dividing values which optimizes a cost function F.