基本信息:

• 专利标题： Method and circuit for determining a slow clock calibration factor
• 专利标题（中）：Verfahren und Anordnung zur Bestimmung eines Kalibrations-Faktorsfüreinen langsamen Takt
• 申请号：EP05252080.6 申请日：2005-04-01
• 公开(公告)号：EP1585223A1 公开(公告)日：2005-10-12
• 发明人： Erdélyi, Jànos , Onody, Péter
• 申请人： Integration Associates Inc.
• 申请人地址： 110 Pioneer Way, Unit L Mountain View, CA 94041 US
• 专利权人： Integration Associates Inc.
• 当前专利权人： Integration Associates Inc.
• 当前专利权人地址： 110 Pioneer Way, Unit L Mountain View, CA 94041 US
• 代理机构： Wilson, Alan Stuart
• 优先权： US819056 20040406
• 主分类号： H03L1/00
• IPC分类号： H03L1/00 ; H04B1/16

摘要：

Shown is a method and circuit for determining a calibration factor between a fast, high accuracy clock signal and a slow, low accuracy clock signal, which can be realised with a minimum number of electronic units, and which obtains the calibration factor in a very short time, thus minimising power consumption of the circuit. The present invention operates by counting the number of cycles of a high accuracy clock signal during a single cycle of a low accuracy clock signal to obtain a first number representing the number of cycles counted and then successively summing the first number until a sum of the first numbers reaches a first predetermined value. The count of the number of summing operations required to reach the first predetermined value is then used to determine the calibration parameter, which is proportional to the number of summing operations.

摘要（中）：

显示了一种用于确定快速，高精度时钟信号与慢速，低精度时钟信号之间的校准因子的方法和电路，该信号可以用最小数量的电子单元实现，并且在非常短的时间内获得校准因子 时间，从而最小化电路的功耗。 本发明通过在低精度时钟信号的单个周期期间对高精度时钟信号的周期数进行计数来进行操作，以获得表示所计数的周期数的第一数字，然后对第一个数字进行连续求和，直到第一个 数字达到第一预定值。 然后使用达到第一预定值所需的求和操作次数的计数来确定与求和操作次数成比例的校准参数。

公开/授权文献:

• EP1585223B1  Method and circuit for determining a slow clock calibration factor 公开/授权日：2007-10-03

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