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1. 发明授权

EP1585223B1 Method and circuit for determining a slow clock calibration factor 有权
标题翻译：方法和装置用于确定一个慢时钟的校准因子
公开(公告)号：EP1585223B1
公开(公告)日：2007-10-03
申请号：EP05252080.6
申请日：2005-04-01
申请人： Integration Associates Inc.
发明人： Erdélyi, Jànos , Onody, Péter
IPC分类号： H03L1/00 , H04B1/16
CPC分类号： H03L1/00

2. 发明公开

EP1630957A1 Tunable poly-phase filter and method for calibration thereof 有权
标题翻译： Abstimmbares Polyphasenfilter und Verfahren zu dessen Kalibrierung
公开(公告)号：EP1630957A1
公开(公告)日：2006-03-01
申请号：EP05255301.3
申请日：2005-08-30
申请人： Integration Associates Inc.
发明人： De Ruijter, Hendricus
IPC分类号： H03H11/04 , H03H11/08
CPC分类号： H03H11/0472 , H03H11/0444 , H03H2011/0494 , H03H2210/012 , H03H2210/015 , H03H2210/017 , H03H2210/021 , H03H2210/04
摘要： A resonator circuit is shown that is fabricated with substantially identical elements disposed symmetrically along an axis such that the circuit has a linear response to bias current. The alignment of the circuit permits multiple characteristics of the circuit to be calibrated.
摘要翻译：示出了谐振器电路，其被制造成具有基本上相同的沿着轴对称设置的元件，使得该电路对偏置电流具有线性响应。电路的对准允许校准电路的多个特性。

3. 发明公开

EP1447961A1 Hook switch circuit and power circuit for electronic telephone line interface 审中-公开
标题翻译： Auflegen Schalterstromkreis und Energiestromkreisfüreine elektronische Fernsprechleitungsschnittstelle
公开(公告)号：EP1447961A1
公开(公告)日：2004-08-18
申请号：EP04003142.9
申请日：2004-02-12
申请人： Integration Associates Inc.
发明人： Holcombe, Wayne T. , Pardoen, Matthijs D.
IPC分类号： H04M1/738
CPC分类号： H04M1/738
摘要： A hook switch circuit is shown wherein two high-voltage bipolar transistors, a PNP transistor (Q1) and a NPN transistor (Q2), that are connected in a regenerative feedback manner to form a bi-stable latch. The regenerative structure permits the use of low beta transistors that may be turned on with a low control current, but still conduct a sufficient off-hook current. Also shown is a polarity steering regenerative switch (MPI, MP2) that provides a power supply voltage from a telephone line pair and may be adapted for a polarity signal and can be combined with a current mirror (MP7) to produce a current signal proportional to the line voltage (LVI).
摘要翻译：示出了钩形开关电路，其中以再生反馈方式连接的两个高电压双极晶体管PNP晶体管（Q1）和NPN晶体管（Q2）形成双稳态锁存器。再生结构允许使用可以以低控制电流导通的低β晶体管，但仍然进行足够的摘机电流。还示出了极性转向再生开关（MPI，MP2），其提供来自电话线对的电源电压，并且可以适用于极性信号，并且可以与电流镜（MP7）组合以产生与线路电压（LVI）。

4. 发明授权

EP1309144B1 Method and apparatus for isolation in a data access arrangement using analog encoded pulse signaling 有权
标题翻译：通过PWM控制来的方法和用于在数据存取装置电线的绝缘装置
公开(公告)号：EP1309144B1
公开(公告)日：2008-03-19
申请号：EP02024427.3
申请日：2002-10-29
申请人： Integration Associates Inc.
发明人： Holcombe, Wayne T. , Pardoen, Matthijs D.
IPC分类号： H04L25/02 , H04M11/06
CPC分类号： H04L25/4902 , H04B14/026 , H04L25/0268

5. 发明公开

EP1583234A3 Tunable sallen-key filter stage and filter assembly 审中-公开
标题翻译：可调的Sallen-Key滤波器和过滤器组件
公开(公告)号：EP1583234A3
公开(公告)日：2006-10-04
申请号：EP05252079.8
申请日：2005-04-01
申请人： Integration Associates Inc.
发明人： Onody, Peter
IPC分类号： H03H11/12 , H03J5/02 , H03K4/502
CPC分类号： H03H11/1291 , H03H11/1286 , H03J2200/10 , H03K3/0231
摘要： Disclosed is a filter circuit assembly that includes a filter stage with a variable resistor and a resistor/capacitor (RC) oscillator. A controlling output of the RC oscillator controls the value of the variable resistor. The RC oscillator itself also includes a variable resistor. The controlling output of the RC oscillator also controls the value of the variable resistor of the RC oscillator. The structure of the variable resistor of the filter stage is substantially the same as the structure of the variable resistor of the RC oscillator.

6. 发明公开

EP1531640A3 Transmitter and receiver circuits comprising an internal controller to establish operating parameters when no external controller is available 有权
标题翻译：发送和接收与内部控制单元电路，用于设置操作参数当没有外部控制单元可用
公开(公告)号：EP1531640A3
公开(公告)日：2005-12-07
申请号：EP04009938.4
申请日：2004-04-27
申请人： Integration Associates Inc.
发明人： Holcombe, Wayne T. , Hegyi, Andras , Keller, Tibor , Horvath, Vince A. , Pardoen, Matthijs D. , Erdélyi, Janos
IPC分类号： H04Q7/32
CPC分类号： H04B1/401
摘要： Transmitter (230) and receiver (250) circuits are shown that are capable of operating in a stand-alone mode without the necessity of an external controller to program the transmitter and receiver circuits, such as by providing operating parameters through a control interface. An internal controller (234) of the transmitter (230) detects that no external controller is present and operates to access an external storage device (210), such as an EEPROM, to obtain data for configuring at least some of the operating characteristics of the transmitter (230). The transmitter (230) may be configured to respond to predetermined events by accessing corresponding data at predetermined addresses of the EEPROM. The internal controller (254) of the receiver (250) may also detect that no external controller is present and to obtain data for configuring at least some of the operating characteristics of the receiver (250). Also, the internal controller (254) of the receiver (250) may be configured to monitor a predetermined communication channel in order to receive operating parameter data and configure the operation of the receiver (250) accordingly. The transmitter (230) may be configured to transmit operating parameter data to the receiver (250) via the predetermined communication channel.

7. 发明公开

EP1585223A1 Method and circuit for determining a slow clock calibration factor 有权
标题翻译： Verfahren und Anordnung zur Bestimmung eines Kalibrations-Faktorsfüreinen langsamen Takt
公开(公告)号：EP1585223A1
公开(公告)日：2005-10-12
申请号：EP05252080.6
申请日：2005-04-01
申请人： Integration Associates Inc.
发明人： Erdélyi, Jànos , Onody, Péter
IPC分类号： H03L1/00 , H04B1/16
CPC分类号： H03L1/00
摘要： Shown is a method and circuit for determining a calibration factor between a fast, high accuracy clock signal and a slow, low accuracy clock signal, which can be realised with a minimum number of electronic units, and which obtains the calibration factor in a very short time, thus minimising power consumption of the circuit. The present invention operates by counting the number of cycles of a high accuracy clock signal during a single cycle of a low accuracy clock signal to obtain a first number representing the number of cycles counted and then successively summing the first number until a sum of the first numbers reaches a first predetermined value. The count of the number of summing operations required to reach the first predetermined value is then used to determine the calibration parameter, which is proportional to the number of summing operations.
摘要翻译：显示了一种用于确定快速，高精度时钟信号与慢速，低精度时钟信号之间的校准因子的方法和电路，该信号可以用最小数量的电子单元实现，并且在非常短的时间内获得校准因子时间，从而最小化电路的功耗。本发明通过在低精度时钟信号的单个周期期间对高精度时钟信号的周期数进行计数来进行操作，以获得表示所计数的周期数的第一数字，然后对第一个数字进行连续求和，直到第一个数字达到第一预定值。然后使用达到第一预定值所需的求和操作次数的计数来确定与求和操作次数成比例的校准参数。

8. 发明公开

EP1450546A2 Method and apparatus for isolation in a caller ID or call monitor interface circuit 审中-公开
标题翻译：用于主叫识别或者电话覆盖接口电路的隔离的方法和装置
公开(公告)号：EP1450546A2
公开(公告)日：2004-08-25
申请号：EP04003839.0
申请日：2004-02-20
申请人： Integration Associates Inc.
发明人： Holcombe, Wayne T. , Konecny, Pavel
IPC分类号： H04M1/57
CPC分类号： H04M1/573
摘要： A caller ID circuit is shown that uses resistors as a caller ID interface to a telephone line pair. The circuit includes a differential transconductance amplifier coupled to the telephone line pair using resistors and a common mode canceling transconductance amplifier coupled to the telephone line pair using the resistors. The invention also includes a gyrator transconductance amplifier coupled to the differential transconductance amplifier and the common mode canceling transconductance amplifier that is configured to generate an output current corresponding to a caller ID signal present at the telephone line pair. In a further refinement of the invention, the resistors are accurate resistors. In another refinement of the invention, the circuit further includes an analog to digital converter (ADC) coupled to the gyrator transconductance amplifier, where the ADC converts the output current from the gyrator transconductance amplifier into a pulse-width-modulated (PWM) signal.
摘要翻译：呼叫者ID电路示那样使用电阻器作为呼叫者ID接口到电话线对。所述电路包括耦合到使用电阻器的电话线对和连接到使用电阻电话线对的共同模式取消跨导放大器的差分跨导放大器。因此本发明包括耦合到所述差分跨导放大器和取消跨导放大器的共模也被配置成在输出电流对应于主叫方ID存在于电话线对的信号，以产生一个回转器跨导放大器。在本发明的进一步改进中，所述电阻器是精确的电阻器。在本发明的另一改进中，所述电路还包括：模拟到耦合到回转器跨导放大器，其中，所述ADC从回转器跨导放大器的输出电流转换成脉冲宽度调制（PWM）信号的数字转换器（ADC）。

9. 发明公开

EP0942472A3 Distributed photodiode and integrated circuit comprising said photodiode and an infrared receiver 有权
标题翻译：分布式光电二极管和集成电路与所述光电二极管和红外线接收器
公开(公告)号：EP0942472A3
公开(公告)日：2002-10-16
申请号：EP99200543.9
申请日：1999-02-25
申请人： Integration Associates, Inc.
发明人： Holcombe, Wayne Thomas
IPC分类号： H01L31/103 , H01L27/144 , H04B10/158 , H01L31/0352 , H01L31/02
CPC分类号： H01L31/02005 , H01L31/0352 , H01L31/103 , H04B10/114 , H04B10/40
摘要： A distributed photodiode (330) is shown having a plurality of doped regions (332) formed in a uniform pattern on a first surface of a semiconductor substrate (210) and interconnected by a plurality of conductive traces (334). The doped regions are minimum geometry dots for a standard semiconductor fabrication process that are spaced apart from one another by an interval that is less than an average distance travelled by photo-generated carriers in the substrate before recombination. A conductive backplane (212) is formed on a second surface of the semiconductor substrate to produce an inverted induced signal for noise cancelling. The distributed photodiode may be part of an integrated circuit (300) comprising an infrared receiver (220).

10. 发明授权

EP1630957B1 Tunable poly-phase filter and method for calibration thereof 有权
标题翻译：可调谐多相滤波器和校准的方法
公开(公告)号：EP1630957B1
公开(公告)日：2007-10-03
申请号：EP05255301.3
申请日：2005-08-30
申请人： Integration Associates Inc.
发明人： De Ruijter, Hendricus
IPC分类号： H03H11/04 , H03H11/08
CPC分类号： H03H11/0472 , H03H11/0444 , H03H2011/0494 , H03H2210/012 , H03H2210/015 , H03H2210/017 , H03H2210/021 , H03H2210/04

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