
基本信息:
- 专利标题: 一种基于忆阻的四位二进制乘法器电路
- 专利标题(英):Memristor-based four-bit binary multiplier circuit
- 申请号:CN201910919319.7 申请日:2019-09-26
- 公开(公告)号:CN110705193A 公开(公告)日:2020-01-17
- 发明人: 王延峰 , 耿盛涛 , 李盼龙 , 梁恩豪 , 杨秦飞 , 杨宇理 , 李智 , 张桢桢 , 孙军伟 , 余培照 , 王英聪 , 黄春 , 方洁 , 张勋才 , 王妍
- 申请人: 郑州轻工业学院
- 申请人地址: 河南省郑州市金水区东风路5号
- 专利权人: 郑州轻工业学院
- 当前专利权人: 郑州轻工业学院
- 当前专利权人地址: 河南省郑州市金水区东风路5号
- 代理机构: 郑州优盾知识产权代理有限公司
- 代理人: 栗改
- 主分类号: G06F30/33
- IPC分类号: G06F30/33 ; H03K19/20
The invention provides a memristor-based four-bit binary multiplier circuit, which comprises a four-bit adder and a multiplication unit. The four-bit adder is connected with the multiplication unit, and the multiplication unit and the four-bit adder are both based on memristors. One group of input ends of the first multiplication unit, the second multiplication unit, the third multiplication unitand the fourth multiplication unit are connected with four input signals of a first multiplier, and the other group of input ends of the first multiplication unit, the second multiplication unit, thethird multiplication unit and the fourth multiplication unit are respectively connected with one input signal of a second multiplier in sequence. The output ends of the first multiplication unit and the second multiplication unit are respectively connected with the first input end and the second input end of the first four-bit adder. The result output by the circuit conforms to the logic functionrealized by the four-bit multiplier, four-bit multiplication operation can be carried out on the signal input into the circuit, and a very large development space can be achieved in the future information technology.
公开/授权文献:
- CN110705193B 一种基于忆阻的四位二进制乘法器电路 公开/授权日:2020-10-02
IPC结构图谱:
G06F30/33 | 设计验证,例如功能仿真或模型检查 |