![针对全环栅极晶体管器件的隔离方案](/CN/2019/1/91/images/201910456790.jpg)
基本信息:
- 专利标题: 针对全环栅极晶体管器件的隔离方案
- 专利标题(英):Isolation schemes for gate-all-around transistor devices
- 申请号:CN201910456790.7 申请日:2019-05-29
- 公开(公告)号:CN110660797A 公开(公告)日:2020-01-07
- 发明人: R.梅汉德鲁 , S.M.策亚 , B.古哈 , T.加尼 , W.徐
- 申请人: 英特尔公司
- 申请人地址: 美国加利福尼亚州
- 专利权人: 英特尔公司
- 当前专利权人: 英特尔公司
- 当前专利权人地址: 美国加利福尼亚州
- 代理机构: 中国专利代理(香港)有限公司
- 代理人: 黄涛; 申屠伟进
- 优先权: 16/024046 2018.06.29 US
- 主分类号: H01L27/088
- IPC分类号: H01L27/088 ; H01L21/8234
Isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons (312), in a targeted channel region (315) between active or functional transistor devices to electrically isolate those active devices. The targeted channel region (315) is referred to herein as a dummy channel region, asit is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons (312, 315) in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L27/00 | 由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件 |
--------H01L27/02 | .包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的;包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的 |
----------H01L27/04 | ..其衬底为半导体的 |
------------H01L27/06 | ...在非重复结构中包括有多个单个组件的 |
--------------H01L27/085 | ....只包含场效应的组件 |
----------------H01L27/088 | .....有绝缘栅场效应晶体管的组件 |