The invention discloses a high-speed floating point unit, which is in an N-level pipeline organization, wherein N is a natural number larger than 1. The high-speed floating point unit comprises an input DFF (D type flip-flop), an operand information extraction and zone bit judgment unit, N-level floating point arithmetic structures and an N-level DFF and data selection unit. The input DFF is connected to a first-level floating point arithmetic structure in the N-level floating point arithmetic structures through the operand information extraction and zone bit judgment unit. The first-level floating point arithmetic structure is connected to a first-level DFF in N-level DFFs, the first-level DFF is connected with a second-level floating point arithmetic structure in the N-level floating point arithmetic structures, the second-level floating point arithmetic structure is connected with a second-level DFF in the N-level DFFs, and the second-level DFF is connected with a third-level floating point arithmetic structure, and so on. An N-1-level DFF is connected with an N-level floating point arithmetic structure in the N-level floating point arithmetic structures, and the N-level floating point arithmetic structure is connected with the N-level DFF in the N-level DFFs through the data selection unit.