专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2013130934A1 SYSTEM FOR A CLOCK SHIFTER CIRCUIT 审中-公开
标题翻译：时钟更换电路系统
公开(公告)号：WO2013130934A1
公开(公告)日：2013-09-06
申请号：PCT/US2013028525
申请日：2013-03-01
申请人： ANALOG DEVICES INC
发明人： DEROUNIAN PETER , BARDSLEY SCOTT
IPC分类号： H03L3/00
CPC分类号： H03K5/135
摘要： A clock shifter circuit may receive a input clock in a first voltage domain and may generate a level-shifted output clock in a second voltage domain. The circuit may include a cross-coupled pair of transistor switches and a pair of capacitors. Each switch may have a drain coupled to one of the capacitors, a source coupled to a circuit supply voltage, and a gate coupled to the other capacitor. One capacitor may receive a true input clock version, while the other may receive a complement version. Each capacitor, in an alternating manner, may activate an opposing transistor switch to charge its capacitor during an active phase of its respective input clock. The circuit may generate the output clock from an output node connected between one of the transistor switches and its capacitor. The output clock may drive a load directly coupled to the output node.
摘要翻译：时钟移位器电路可以在第一电压域中接收输入时钟，并且可以在第二电压域中产生电平移位的输出时钟。电路可以包括交叉耦合的一对晶体管开关和一对电容器。每个开关可以具有耦合到电容器之一的漏极，耦合到电路电源电压的源极和耦合到另一个电容器的栅极。一个电容器可以接收真实的输入时钟版本，而另一个可以接收补码版本。每个电容器以交替方式可以激活相对的晶体管开关，以在其相应的输入时钟的有效相位期间对其电容器充电。该电路可以从连接在一个晶体管开关及其电容器之间的输出节点产生输出时钟。输出时钟可以驱动直接耦合到输出节点的负载。

2. 发明申请

WO2013085579A3 RESONANT OSCILLATOR WITH START UP AND SHUT DOWN CIRCUITRY 审中-公开
公开(公告)号：WO2013085579A3
公开(公告)日：2013-06-13
申请号：PCT/US2012/052464
申请日：2012-08-27
申请人： APPLE INC. , CHOU, Catherine S. , ATHAS, William C. , SULLENS, Heather R.
发明人： CHOU, Catherine S. , ATHAS, William C. , SULLENS, Heather R.
IPC分类号： H03L3/00 , H03B5/06
摘要： The disclosed embodiments provide a system which starts up and shuts down a resonant oscillator circuit. During the start up process, a driving circuit uses a first clock signal to control a first phase output of the resonant oscillator circuit. At the same time, the driving circuit uses a second clock signal to control a second phase output of the resonant oscillator circuit, wherein the first and second clock signals have opposite phases. While the first and second phase outputs are being controlled, the system ramps up an input voltage, which is used to power the resonant oscillator circuit, wherein the ramping takes place across multiple initial oscillation periods. During the shut down process, the system shuts down the resonant oscillator circuit by ramping down the input voltage. After the input voltage has been ramped down, the system clamps the first and second phase outputs to a fixed voltage.

3. 发明申请

WO2007060210A1 OSCILLATOR COMPRISING A STARTUP CONTROL DEVICE 审中-公开
标题翻译：包含启动控制设备的振荡器
公开(公告)号：WO2007060210A1
公开(公告)日：2007-05-31
申请号：PCT/EP2006/068852
申请日：2006-11-23
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) , ISBERG, Martin
发明人： ISBERG, Martin
IPC分类号： H03B5/06 , H03L3/00
CPC分类号： H03B5/06 , H03B5/1209 , H03B5/1228 , H03B5/1231 , H03B5/1253 , H03B5/1265 , H03B5/368 , H03B2200/0094 , H03J5/244 , H03L3/00
摘要： An oscillator device (1) comprises an oscillator core (2), a capacitive loading unit (3, 3a, 3b) having a controllable capacitance value and being connected to the oscillator core (2), and a memory device (4) including a first and a second memory unit (5a, 5b) and being connected to the capacitive loading unit. The first memory unit (5a) is adapted to store a first value to be supplied to the capacitive loading unit (3, 3a, 3b) for controlling the capacitance value during a start-up time period. The second memory unit (5b) is adapted to store a second value to be supplied to the capacitive loading unit (3, 3a, 3b) for controlling the capacitance value during an operational time period. According to a method for start up of the oscillator device (1), the amplitude of an oscillator signal is measured. Further, the starting-time instant for the operational time period is chosen as the time instant when the oscillator signal exceeds a predetermined threshold value.
摘要翻译：振荡器装置（1）包括振荡器芯（2），具有可控电容值的电容性负载单元（3,3a，3b），并连接到振荡器芯（2）;以及存储器件（4）第一和第二存储单元（5a，5b），并连接到电容性负载单元。第一存储器单元（5a）适于存储要提供给电容性负载单元（3,3a，3b）的第一值，用于在启动时段期间控制电容值。第二存储器单元（5b）适于存储要提供给电容性负载单元（3,3a，3b）的第二值，用于在操作时间段期间控制电容值。根据振荡器装置（1）的启动方法，测量振荡信号的振幅。此外，选择操作时间段的起始时刻作为振荡器信号超过预定阈值的时刻。

4. 发明申请

WO01056008A1 POINTING DEVICE WITH Z-AXIS FUNCTIONALITY AND REDUCED COMPONENT COUNT 审中-公开
标题翻译：具有Z轴功能和减少组件计数的指示装置
公开(公告)号：WO01056008A1
公开(公告)日：2001-08-02
申请号：PCT/US2001/002389
申请日：2001-01-24
IPC分类号： G05G9/047 , G06F1/32 , G06F3/038 , H02J7/00 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , G09G5/08
CPC分类号： G06F3/0383 , G05G9/047 , G05G2009/04777 , G06F1/3203 , G06F1/3237 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , Y02D10/128
摘要： Apparatus and method are disclosed for receiving human input by means of a pointing device, typically a strain gauge (72, 73, 74, 75). Three dimensions of input are received from a resistor bridge (1) by means of four contact points to the strain gauge (72, 73, 74, 75). A sequence of excitation signals is applied to the bridge (1) and a multiplexer (12) is employed to permit a signal processor (30) to sample sensor outputs. The apparatus processes the sampled outputs and determines the user inputs such as X and Y and Z values of the pointing device.
摘要翻译：公开的装置和方法用于通过指示装置（通常为应变仪（72,73,74,75））接收人的输入。输入的三个尺寸通过四个接触点从应变仪（72,73,74,75）从电阻桥（1）接收。激励信号的序列被施加到桥（1），并且使用多路复用器（12）来允许信号处理器（30）对传感器输出进行采样。该装置处理采样的输出并确定诸如指示装置的X和Y和Z值的用户输入。

5. 发明申请

WO2005109732A8 LOW POWER DIRECT CONVERSION RF TRANSCEIVER ARCHITECTURE AND ASIC AND SYSTEMS INCLUDING SUCH 审中-公开
标题翻译：低功率直接转换射频收发器架构以及包含这些功能的ASIC和系统
公开(公告)号：WO2005109732A8
公开(公告)日：2007-10-25
申请号：PCT/US2005015160
申请日：2005-05-02
申请人： CUSTOM ONE DESIGN INC , NUYTKENS PETER R , KULINETS JOSEPH M
发明人： NUYTKENS PETER R , KULINETS JOSEPH M
IPC分类号： G05F1/00 , G05F1/24 , G05F1/247 , H03L3/00 , H03L7/24 , H04B1/30 , H04L7/02 , H04L27/12
CPC分类号： H04B1/30 , H03L3/00 , H03L7/24 , H04L27/12 , Y10T307/696
摘要： A direct conversion RF transceiver (2) and ASIC having an on-chip voltage controlled oscillator operating frequency that is half of the transmitter (4) and/or receiver (6) operating frequency, the VCO (20) being comprised of a plurality of synchronized LC oscillators (92A-D) introducing precise phase shifts that eliminate frequency ambiguity. The transceiver incorporates several low power circuits, including on-chip a power converter switchably coupling a capacitor (42) to a power supply (45) and to an electrical load (40), multiple switchable low dropout regulators (60A, B) each coupled to alternate power supplies (62, 64) and having electrical components (67A, B) for setting the bandwidth of the respective low dropout regulator. The transceiver also includes a FSK digital modulator utilizing a circuit-implemented polynomial piecewise approximation (71) of a raised cosine signal.
摘要翻译：一种具有作为发射器（4）和/或接收器（6）工作频率的一半的片上压控振荡器工作频率的直接转换RF收发器（2）和ASIC，所述VCO（20）由多个同步LC振荡器（92A-D）引入精确的相移，消除频率模糊。该收发机包含多个低功率电路，包括片上功率转换器，可切换地将电容器（42）耦合到电源（45）和电负载（40），多个可切换的低压差稳压器（60A，B）交替电源（62,64）并且具有用于设置相应的低压差调节器的带宽的电气部件（67A，B）。收发器还包括利用升余弦信号的电路实现的多项式分段近似（71）的FSK数字调制器。

6. 发明申请

WO01078237A1 FAST RAMPING OF CONTROL VOLTAGE WITH ENHANCED RESOLUTION 审中-公开
标题翻译：控制电压快速放大与增强分辨率
公开(公告)号：WO01078237A1
公开(公告)日：2001-10-18
申请号：PCT/US2001/006879
申请日：2001-03-05
IPC分类号： H03L3/00 , H03L7/093 , H03L7/14 , H03L7/189
CPC分类号： H03L3/00
摘要： A logic circuit for generating a control voltage includes a ramp DAC and a main DAC. When the control voltage is needed, such as when an associated crystal oscillator is being "turned on", an input reference voltage is supplied to both the ramp DAC and the main DAC. The ramp DAC generates an output based on the input reference voltage and L supplied control bits for a (preferably short) ramp time period. The output from the ramp DAC is fed to a filter circuit that includes a capacitor to charge the capacitor and the control voltage is generated at least in part from the ramp DAC output as filtered by the capacitor. When the ramp period ends, the state of the input reference voltage is changed and the output from the main DAC, based on the changed input reference voltage and N control bits, is input to the filter. Such a two DAC arrangement allows for a shorter time constant circuit to be employed in association with the ramp DAC and a longer time constant circuit to be employed in association with the main DAC, allowing for quick ramp up of the control voltage. By adjusting the input reference voltage when supplied to the ramp DAC during the ramp period, as compared with when supplied to the main DAC after the ramp period, the circuit allows emulation of greater than L-bit control for the ramp DAC. Thus, the output of the ramp DAC may be more closely "tuned" to the output of the main DAC without increasing the number of control bits supplied to the ramp DAC.
摘要翻译：用于产生控制电压的逻辑电路包括斜坡DAC和主DAC。当需要控制电压时，例如当相关的晶体振荡器“接通”时，输入参考电压被提供给斜坡DAC和主DAC两者。斜坡DAC基于输入参考电压和L（提供的）控制位产生一个（优选短的）斜坡时间周期的输出。来自斜坡DAC的输出被馈送到包括电容器以对电容器充电的滤波器电路，并且至少部分地由电容器滤波的斜坡DAC输出产生控制电压。当斜坡期结束时，输入参考电压的状态改变，基于改变的输入参考电压和N个控制位的主DAC的输出被输入到滤波器。这种两个DAC布置允许与斜坡DAC相关联地使用更短的时间常数电路，并且与主DAC相关联地使用更长的时间常数电路，从而允许控制电压的快速上升。通过在斜坡期间提供给斜坡DAC时调整输入参考电压，与在斜坡周期后提供给主DAC的情况相比，该电路允许对斜坡DAC进行大于L位控制的仿真。因此，斜坡DAC的输出可以更加紧密地“调谐”到主DAC的输出，而不增加提供给斜坡DAC的控制位的数量。

7. 发明申请

WO01056062A2 CHARGE BALANCING SYSTEM 审中-公开
标题翻译：充电平衡系统
公开(公告)号：WO01056062A2
公开(公告)日：2001-08-02
申请号：PCT/US2001/002391
申请日：2001-01-24
IPC分类号： G05G9/047 , G06F1/32 , G06F3/038 , H02J7/00 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , H01L
CPC分类号： G06F3/0383 , G05G9/047 , G05G2009/04777 , G06F1/3203 , G06F1/3237 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , Y02D10/128
摘要： The problem of battery failure due to failure of one cell in a rechargeable battery, and the related problem of inefficient use of a battery over its dynamic range due to differences between the performance of cells in a battery, are addressed by providing one or more capacitors selectively coupled to the various cells of the battery. The selective and repetitive coupling of capacitors to the cells permits balancing of charge among the cells. This minimizes the risk that any one cell would suffer catastrophic failure due to being fully charged or discharged prior to the other cells in the battery. This also permits making use of the battery over nearly all of its dynamic range. In this way, battery life is maximized.
摘要翻译：由于可再充电电池中的一个电池的故障导致的电池故障的问题以及由于电池中的电池的性能之间的差异而在其动态范围内低效使用电池的相关问题通过提供一个或多个电容器选择性地耦合到电池的各个单元。电容器与电池的选择性和重复耦合允许电池间的电荷平衡。这使得任何一个电池由于在电池中的其它电池之前被完全充电或放电而遭受灾难性故障的风险最小化。这也允许在几乎所有动态范围内使用电池。以这种方式，电池寿命最大化。

8. 发明申请

WO00076070A1 INDUCTIVE PROXIMITY SENSOR OSCILLATOR 审中-公开
标题翻译：电感式传感器振荡器
公开(公告)号：WO00076070A1
公开(公告)日：2000-12-14
申请号：PCT/US2000/015074
申请日：2000-06-01
IPC分类号： H03K3/014 , H03K3/0231 , H03K17/95 , H03L3/00
CPC分类号： H03K17/9547 , H03K3/014 , H03K3/0231 , H03L3/00
摘要： An inductive proximity sensor oscillator (A) having a differential comparator (38) in combination with a negative feedback network (38) and a positive feedback network connected to the comparator. The positive feedback network (22, 36) determines the frequency and amplitude of the generated oscillations. An LC resonant tank circuit (22) is connected between a non-inverting input (30) and a fixed reference voltage (20), and a current limiting resistor (36) connected between the non-inverting input and the output of the comparator. The negative feedback network (38) provides a simple, fast and reliable start-up mechanism. It comprises a capacitor (40) connected between the inverting input of the comparator and the circuit ground and a resistor (42)
摘要翻译：具有与负反馈网络（38）组合的差分比较器（38）和连接到比较器的正反馈网络的电感式接近传感器振荡器（A）。正反馈网络（22,36）确定产生的振荡的频率和振幅。 LC谐振回路（22）连接在同相输入（30）和固定基准电压（20）之间，以及连接在同相输入与比较器的输出之间的限流电阻（36）。负反馈网络（38）提供了一种简单，快速和可靠的启动机制。其包括连接在比较器的反相输入端和电路接地之间的电容器（40）和电阻器（42）

9. 发明申请

WO9637960A3 CONFIGURABLE POWER MANAGEMENT SCHEME 审中-公开
标题翻译：可配置电源管理方案
公开(公告)号：WO9637960A3
公开(公告)日：1997-02-06
申请号：PCT/US9607571
申请日：1996-05-23
申请人： NAT SEMICONDUCTOR CORP
发明人： SHAY MICHAEL J
IPC分类号： G06F1/04 , G06F1/06 , G06F1/08 , G06F1/24 , G06F1/32 , H03L3/00
CPC分类号： G06F1/324 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/24 , G06F1/3203 , H03L3/00 , Y02D10/126
摘要： A power management system pad clock and self-test circuit includes a clock processing circuit having a input configured to receive an oscillator clock signal having a first frequency. The clock processing circuit is configured to generate a first pad clock signal having a frequency approximately equal to one-half the first frequency and a second pad clock signal having a frequency that is equal to a programmable fraction of the first frequency. The circuit also includes a main pad clock output node. Multiplexer circuitry is coupled to the clock processing circuitry and the main pad clock output node and configured to receive a plurality of peripheral signals. The multiplexer circuitry is configured to operate in a standard mode of operation wherein one of the first pad clock signal and the second pad clock signal is routed to the main pad clock output node and a first test mode of operation wherein one of the plurality of peripheral signals is selectably routed to the main pad clock output node.
摘要翻译：电源管理系统焊盘时钟和自检电路包括具有被配置为接收具有第一频率的振荡器时钟信号的输入的时钟处理电路。时钟处理电路被配置为产生具有大致等于第一频率的一半的频率的第一焊盘时钟信号和具有等于第一频率的可编程分数的频率的第二焊盘时钟信号。电路还包括主焊盘时钟输出节点。多路复用器电路耦合到时钟处理电路和主时钟输出节点并被配置为接收多个外围信号。多路复用器电路被配置为在标准操作模式下操作，其中第一焊盘时钟信号和第二焊盘时钟信号之一被路由到主焊盘时钟输出节点和第一测试操作模式，其中多个外围设备之一信号可选地路由到主焊盘时钟输出节点。

10. 发明申请

WO2015185103A1 OSCILLATOR CIRCUIT WITH BIAS CURRENT GENERATOR 审中-公开
标题翻译：具有偏置电流发生器的振荡器电路
公开(公告)号：WO2015185103A1
公开(公告)日：2015-12-10
申请号：PCT/EP2014/061407
申请日：2014-06-02
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
发明人： PELTONEN, Janne Olavi , ELGAARD, Christian , STENMAN, Anna Karin
IPC分类号： H03B5/32 , H03L3/00 , H03L5/00
CPC分类号： H03L3/00 , H03B5/32 , H03B2200/0012 , H03B2200/0062 , H03B2200/0066 , H03B2200/0082 , H03B2200/0094 , H03L5/00
摘要： An oscillator circuit (100) comprises a crystal oscillator (10) arranged to generate an oscillation signal, a bias current generator (20) arranged to supply a bias current to the crystal oscillator (10), and a feedback stage (30) arranged to generate a feedback signal in response to an amplitude of the oscillation signal reaching an amplitude threshold. The bias current generator (20) is arranged to: in response to a supply of power to the oscillator circuit (100) being switched on, generate the bias current at an increasing level commencing from a first level; in response to the feedback signal, terminate the increasing; and during subsequent oscillation of the crystal oscillator (10), supply the bias current at a second level dependent on a final level of the bias current reached when the increasing is terminated.
摘要翻译：振荡器电路（100）包括被配置为产生振荡信号的晶体振荡器（10），被布置成向晶体振荡器（10）提供偏置电流的偏置电流发生器（20），以及反馈级响应于振荡信号的振幅达到振幅阈值而产生反馈信号。偏置电流发生器（20）被布置为：响应于向振荡器电路（100）供电的供电，从第一电平开始以增加的电平产生偏置电流; 响应于反馈信号，终止增加; 并且在晶体振荡器（10）的后续振荡期间，根据终止增加时达到的偏置电流的最终电平，将偏置电流提供在第二电平。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式