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1. 发明申请

WO2021035002A1 COMPARATOR HYSTERESIS CIRCUIT 审中-公开
公开(公告)号：WO2021035002A1
公开(公告)日：2021-02-25
申请号：PCT/US2020/047102
申请日：2020-08-20
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： SAKURAI, Satoshi
IPC分类号： H03K5/08 , H03K17/30 , H03K5/125 , H03K3/00
摘要： A comparator circuit includes a first transistor (206), a second transistor (208), a first switch (210), a second switch (212), and a timing circuit. The first transistor (206) and the second transistor (208) are coupled as a differential pair and are configured to compare an input signal to a hysteresis voltage. The first switch (210) is coupled to the first transistor (206) and is configured to selectably enable the first transistor (206). The second switch (212) coupled to the second transistor (208) and is configured to selectably enable the second transistor (208). The timing circuit is coupled to the first switch (210) and the second switch (212) and is configured to close the first switch (210) responsive to a signal transition at an output of the comparator circuit and close the second switch (212) a predetermined delay time after the first switch (210) is closed.

2. 发明申请

WO2021003319A1 NANOSECOND PULSER RF ISOLATION 审中-公开
公开(公告)号：WO2021003319A1
公开(公告)日：2021-01-07
申请号：PCT/US2020/040579
申请日：2020-07-01
申请人： EAGLE HARBOR TECHNOLOGIES. INC
发明人： BOWMAN, Christopher , LISTON, Connor , YANG, Nicolas A. , MILLER, Kenneth , SLOBODOV, Ilia , ZIEMBA, Timothy
IPC分类号： H01J37/32 , H01J37/00 , H03K3/00
摘要： Some embodiments include a plasma system that includes a plasma chamber; an RF driver driving RF bursts into the plasma chamber with an RF frequency greater than 2 MFiz; a nanosecond pulser driving pulses into the plasma chamber with a pulse repetition frequency a peak voltage, the pulse repetition frequency being less than the RF frequency and the peak voltage being greater than 2 kV; a first filter disposed between the RF driver and the plasma chamber; and a second filter disposed between the nanosecond pulser and the plasma chamber.

3. 发明申请

WO2020018716A9 NON-RECIPROCAL TRANSCEIVER ARRAY ARCHITECTURE WITH A SINGLE NON-RECIPROCAL ELEMENT 审中-公开
公开(公告)号：WO2020018716A9
公开(公告)日：2020-01-23
申请号：PCT/US2019/042281
申请日：2019-07-17
申请人： CALIFORNIA INSTITUTE OF TECHNOLOGY
发明人： PORSANDEH KHIAL, Parham , FATEMI, Seyed Mohammadreza , WHITE, Alexander D. , HAJIMIRI, Seyed Ali
IPC分类号： H03K3/00 , H04L7/00 , H04L25/02 , H04L27/00
摘要： A communicate device includes transmitters and a receiver. The first transmitter is coupled to a first 90º phase shifter that is also coupled to a first antenna, and to a second 90º phase shifter that is also coupled to a first node. The second transmitter is coupled to a third 90º phase shifter that is also coupled to a second antenna, and to a fourth 90º phase shifter that is also coupled to the first node. The receiver is coupled to a fifth 90º phase shifter that is also coupled to the first antenna, and to a sixth 90º phase shifter that is also coupled to the second antenna. A non-reciprocal element, coupled between the receiver and the first node, provides a 90º phase shift from the receiver to the first node and a -90º phase shift from the first node to the receiver.

4. 发明申请

WO2019209556A1 TOMOGRAPHIC SYSTEMS AND METHODS FOR DETERMINING CHARACTERISTICS OF INHOMOGENOUS SPECIMENS USING GUIDED ELECTROMAGNETIC FIELDS 审中-公开
公开(公告)号：WO2019209556A1
公开(公告)日：2019-10-31
申请号：PCT/US2019/027327
申请日：2019-04-12
申请人： SPECTROHM, INC.
发明人： CARGOL, Timothy L.
IPC分类号： G01N27/00 , G01N27/02 , G01N27/22 , G01R27/00 , G01R27/26 , H03K3/00
摘要： A system for determining characteristics of a specific region within an inhomogeneous dielectric specimen by guiding propagation of electric fields through the inhomogeneous dielectric specimen is provided herein. Various embodiments include at least one source of electromagnetic energy for generating electromagnetic waveforms, the electromagnetic waveforms comprising electric fields propagating along a prescribed path that defines a series of spatial regions through which the electric fields propagate. In some embodiments the prescribed path includes electric field modulating elements that determine a rate of electric field propagation along the prescribed path. Some embodiments include a plurality of conductors for guiding the electric field propagation through an inhomogeneous dielectric specimen in the prescribed path, the electric fields spanning between two or more of the plurality of conductors as the electric fields propagate along the prescribed path. In some embodiments the plurality of conductors are external to the inhomogeneous dielectric specimen.

5. 发明申请

WO2019142203A1 DIGITAL CIRCUITS FOR RADICALLY REDUCED POWER AND IMPROVED TIMING PERFORMANCE ON ADVANCED SEMICONDUCTOR MANUFACTURING PROCESSES 审中-公开
公开(公告)号：WO2019142203A1
公开(公告)日：2019-07-25
申请号：PCT/IN2018/050121
申请日：2018-03-06
申请人： REZONENT MICROCHIPS PVT. LTD.
发明人： BEZZAM, Ignatius , RAWAT, Neelam
IPC分类号： H04B1/04 , H03K3/00 , G06F1/02 , G06F17/50
摘要： Disclosed is a resonant circuit and method for matched clock and data timing performance for improving timing closure of digital circuits on advanced semiconductor manufacturing processes. The matched resonance circuit comprises pulse generator circuit (202) and plurality of generating latches (206A-N) and plurality of sampling latches (304A-N). The pulse generator circuit (202) comprises plurality of inverters (210A-N), optimum resistance (214) and exclusive OR (Ex-OR) gate (218) which are connected in series and a matched capacitance. The pulse generator circuit (202) generates timing pulse output using one or more buffers and clock inductor. Each generating latch receives clock timing pulse output as timing pulse into plurality of sampling flip-flop latches (304A-N) through clock sample path (CS) to match arrival of timing pulse and outputs of plurality of input data lines that are resonated by connecting one or more of respective load capacitances with at least one shared inductor (208).

6. 发明申请

WO2019097532A9 AN ELECTRONIC CIRCUIT FOR PERFORMING ANY DETERMINISTIC LOGIC GATE FUNCTIONS ON BINARY ELECTRONIC SIGNALS 审中-公开
公开(公告)号：WO2019097532A9
公开(公告)日：2019-05-23
申请号：PCT/IN2018/000052
申请日：2018-11-05
申请人： SINHA, Arnab
发明人： SINHA, Arnab
IPC分类号： H03K3/00

7. 发明申请

WO2017124094A1 SYSTEMS AND METHODS FOR RING-OSCILLATOR BASED OPERATIONAL AMPLIFIERS FOR SCALED CMOS TECHNOLOGIES 审中-公开
标题翻译：用于缩放CMOS技术的基于环形振荡器的运算放大器的系统和方法
公开(公告)号：WO2017124094A1
公开(公告)日：2017-07-20
申请号：PCT/US2017/013768
申请日：2017-01-17
申请人： SEAMLESS DEVICES, INC.
发明人： KUPPAMBATTI, Jayanth
IPC分类号： H03K3/00 , H03F3/00 , H03F3/45 , H03K3/02
CPC分类号： H03F1/0205 , H03F1/56 , H03F3/193 , H03F3/21 , H03F3/45179 , H03F2200/387 , H03F2200/451 , H03K3/0315 , H03K3/0322
摘要： An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs and a second oscillator having an input and N outputs. The amplifier includes N phase detectors, each phase detector has a first input, a second input, a first output, and a second output, where each first input of each phase detector is coupled to respective one of the N outputs of the first oscillator, where each second input of each phase detector is coupled to respective one of the N outputs of the second oscillator. The amplifier includes N quantizers, each quantizer has a data input, a clock input, and an output, where each data input of each quantizer is coupled to respective one first output or one second output of the N phase detectors.
摘要翻译：一种面积有效的放大器，用于放大连续时间连续幅度信号并将其转换为离散时间离散幅度信号。放大器包括具有输入和多个N输出的第一振荡器以及具有输入和N输出的第二振荡器。该放大器包括N个相位检测器，每个相位检测器具有第一输入，第二输入，第一输出和第二输出，其中每个相位检测器的每个第一输入耦合到第一振荡器的N个输出中相应的一个，其中每个相位检测器的每个第二输入端耦合到第二振荡器的N个输出端中的相应一个输出端。该放大器包括N个量化器，每个量化器具有数据输入，时钟输入和输出，其中每个量化器的每个数据输入端耦合到N个相位检测器的相应一个第一输出或一个第二输出。

8. 发明申请

WO2016209387A1 CLOCK DISTRIBUTION SYSTEM 审中-公开
标题翻译：时钟分配系统
公开(公告)号：WO2016209387A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/031755
申请日：2016-05-11
申请人： NORTHROP GRUMMAN SYSTEMS CORPORATION
发明人： STRONG, Joshua A. , HERR, Anna Y. , HERR, Quentin P. , SHAUCK, Steven B.
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： One embodiment includes a clock distribution system. The system includes a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal. The standing-wave resonator includes at least one anti-node portion associated with a peak current amplitude of the sinusoidal clock signal. The system also includes at least one clock line interconnecting each of the at least one anti-node portion and an associated circuit. The at least one clock line can be configured to propagate the sinusoidal clock signal for timing functions associated with the associated circuit.
摘要翻译：一个实施例包括时钟分配系统。该系统包括被配置为接收和谐振正弦时钟信号的驻波谐振器。驻波共振器包括与正弦时钟信号的峰值电流幅度相关联的至少一个反节点部分。该系统还包括互连至少一个反节点部分和相关电路中的每一个的至少一个时钟线。至少一个时钟线可被配置为传播用于与相关电路相关联的定时功能的正弦时钟信号。

9. 发明申请

WO2012115900A2 DRIVER CIRCUIT FOR A SEMICONDUCTOR POWER SWITCH 审中-公开
标题翻译：用于半导体电源开关的驱动电路
公开(公告)号：WO2012115900A2
公开(公告)日：2012-08-30
申请号：PCT/US2012/025803
申请日：2012-02-20
申请人： DEERE & COMPANY , CLEMENTS, Neal, D.
发明人： CLEMENTS, Neal, D.
IPC分类号： H03K3/00
CPC分类号： H03K19/01 , H03K3/356113 , H03K17/164 , H03K19/0175
摘要： A driver circuit (10) for controlling a semiconductor power switch (Q7) comprises a first power driver transistor (QS) and a second power driver transistor (Q5) complementary to the first power driver transistor (08). Both power driver transistors (Q5, Q6) have an output terminal connected to an input terminal {34} of the semiconductor power switch (Q7). An input terminal of the second power driver transistor (Q5) is connected to a half bridge circuit comprising a; first pre-driver transistor (Q3) and a second pre-driver transistor (04) complementary to the first pre-driver transistor
摘要翻译：用于控制半导体功率开关（Q7）的驱动电路（10）包括与第一功率驱动晶体管（08）互补的第一功率驱动晶体管（QS）和第二功率驱动晶体管（Q5）。两个功率驱动晶体管（Q5，Q6）都具有连接到半导体功率开关（Q7）的输入端子（34）的输出端子。第二功率驱动晶体管（Q5）的输入端连接到包括a的半桥电路; 第一预驱动晶体管（Q3）和与第一预驱动晶体管

10. 发明申请

WO2007033045A3 STACKED MOSFETS 审中-公开
标题翻译：堆叠MOSFET
公开(公告)号：WO2007033045A3
公开(公告)日：2009-06-04
申请号：PCT/US2006035227
申请日：2006-09-08
申请人： IDAHO RES FOUND , MENTZE ERIK J , HESS HERBERT L , PHILLIPS JENNIFER E
发明人： MENTZE ERIK J , HESS HERBERT L , PHILLIPS JENNIFER E
IPC分类号： G05F3/16 , H03K3/00
CPC分类号： H03K17/102
摘要： A stacked MOSFET includes a first transistor or MOSFET (202) connected to a bias voltage through bias resistor Rbias.The gate of transistor (202) is grounded through a capacitor (206) The output of the stacked MOSFET arrangement is taken across a plurality of resistors R. An input transistor (204) is connected as shown to receive an input signal Vin.
摘要翻译：堆叠MOSFET包括通过偏置电阻器Rbias连接到偏置电压的第一晶体管或MOSFET（202）。晶体管（202）的栅极通过电容器（206）接地。堆叠MOSFET装置的输出跨越多个电阻器R.如图所示，输入晶体管（204）被连接以接收输入信号Vin。

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