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1. 发明申请

WO2009102948A3 THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE 审中-公开
标题翻译： THRESHOLD逻辑元件具有低漏电和高性能
公开(公告)号：WO2009102948A3
公开(公告)日：2009-10-08
申请号：PCT/US2009034044
申请日：2009-02-13
申请人： UNIV ARIZONA STATE , LESHNER SAMUEL , VRUDHULA SARMA
发明人： LESHNER SAMUEL , VRUDHULA SARMA
IPC分类号： H03K19/08 , G06F7/02 , G06N3/063
CPC分类号： H03K19/0813
摘要： Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology.
摘要翻译：提供阈值逻辑元件的实施例。优选地，本文讨论的阈值逻辑元件的实施例具有低泄漏功率和高性能特性。在优选实施例中，阈值逻辑元件是阈值逻辑锁存器（TLL）。 TLL是一种动态操作的电流模式阈值逻辑单元，可快速有效地实现数字逻辑功能。 TLL可以同步或异步操作，并与标准互补金属氧化物半导体（CMOS）技术完全兼容。

2. 发明申请

WO2005006443A8 LOGIC GATE WITH A POTENTIAL-FREE GATE ELECTRODE FOR ORGANIC INTEGRATED CIRCUITS 审中-公开
标题翻译：用于有机集成电路的无电位栅极电极的逻辑门
公开(公告)号：WO2005006443A8
公开(公告)日：2005-07-07
申请号：PCT/DE2004001376
申请日：2004-06-30
申请人： POLYIC GMBH & CO KG , GLAUERT WOLFRAM , FIX WALTER , ULLMANN ANDREAS
发明人： GLAUERT WOLFRAM , FIX WALTER , ULLMANN ANDREAS
IPC分类号： H01L27/28 , H03K19/094 , H01L27/00 , H03K19/02 , H03K19/08
CPC分类号： H03K19/094 , H01L27/28
摘要： The invention relates to an organic logic gate comprising at least one charging field effect transistor (charging FET) and at least one switching field effect transistor (switching FET), said charging FET comprising at least one gate electrode, a source electrode and a drain electrode, the gate electrode of the charging FET being potential-free.
摘要翻译：本发明涉及具有至少一个充电场效应晶体管（充电FET）和至少一个开关场效应晶体管（开关FET）的有机逻辑门，其中充电FET具有至少一个栅电极，源电极和漏电极其中充电FET的栅极电极是浮置的。

3. 发明申请

WO0122591A9 TWO-STAGE MULLER C-ELEMENT 审中-公开
标题翻译：两阶段MULLER C-ELEMENT
公开(公告)号：WO0122591A9
公开(公告)日：2002-11-14
申请号：PCT/US0026379
申请日：2000-09-25
申请人： SUN MICROSYSTEMS INC , FAIRBANKS SCOTT M
发明人： FAIRBANKS SCOTT M
IPC分类号： G06F9/38 , H03K19/20 , H03K19/177 , G06F1/10 , G06F11/20 , G11C5/00 , H03K19/003 , H03K19/08
CPC分类号： H03K19/20 , G06F9/3869
摘要： A Muller C-element comprises two stages. The first stage consists of a NAND and a NOR gate, each driven by all of the inputs to the Muller C-element. In the second stage, the outputs of the two gates are used separately to switch on and off two output transistors, which drive the output of the Muller C-element. A keeper flip flop serves to retain the output value between changes. Because current from each gate is applied only to one output transistor, delay is reduced. Furthermore, an unneeded output transistor is switched off as soon as logically possible, often during the otherwise unused interval while the input values differ, which reduces both delay and crossover current. In a preferred embodiment, the NAND and NOR gates each comprise a set of series transistors and a set of parallel transistors. The parallel transistors in these gates work together to change the output value when all inputs are changing simultaneously, thereby allowing the use of parallel transistors having widths narrower than those normally employed in NAND and NOR gates. Use of smaller transistors renders the inputs easier to drive, improving the speed of the circuit.
摘要翻译： Muller C元素包括两个阶段。第一级由NAND和NOR门组成，每一个都由Muller C元素的所有输入驱动。在第二级中，两个门的输出分别用于接通和关断驱动Muller C元件输出的两个输出晶体管。保持器触发器用于保持更改之间的输出值。因为来自每个栅极的电流仅施加到一个输出晶体管，所以延迟减小。此外，不需要的输出晶体管一经逻辑地切断，通常在另外未使用的间隔期间，而输入值不同，这减少了延迟和交叉电流。在优选实施例中，NAND和NOR门各自包括一组串联晶体管和一组并联晶体管。当所有输入同时变化时，这些门中的并联晶体管一起工作以改变输出值，从而允许使用宽度窄于NAND和NOR门中通常采用的宽度的并行晶体管。使用更小的晶体管使输入更容易驱动，提高电路的速度。

4. 发明申请

WO01043287A1 METHOD AND APPARATUS FOR AN N-NARY LOGIC CIRCUIT 审中-公开
标题翻译：用于N / N逻辑电路的方法和装置
公开(公告)号：WO01043287A1
公开(公告)日：2001-06-14
申请号：PCT/US1999/029409
申请日：1999-12-10
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21 , H03K19/094
CPC分类号： G06F1/08 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215
摘要： The present invention is a method and apparatus (106) for an N-NARY logic circuit that uses N-NARY signals (A0-A3, B0-B3). The present invention includes a shared logic tree circuit (107) that evaluates one or more N-NARY input signals and produces an N-NARY output signal (V0-V3). The present invention additionally includes a first N-NARY input signal (A0-A3) coupled to the shared logic tree circuit and a second N-NARY input signal (B0-B3) coupled to the shared logic tree circuit. The shared logic circuit evaluates the first and second N-NARY input signal and produces an N-NARY output signal (V0-V3) coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals (A0-A3, B0-B3), 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.
摘要翻译：本发明是一种使用N-NARY信号（A0-A3，B0-B3）的N-NARY逻辑电路的方法和装置（106）。本发明包括共享逻辑树电路（107），其评估一个或多个N-NARY输入信号并产生N-NARY个输出信号（V0-V3）。本发明还包括耦合到共享逻辑树电路的第一N-NARY输入信号（A0-A3）和耦合到共享逻辑树电路的第二N-NARY输入信号（B0-B3）。共享逻辑电路评估第一和第二N-NARY输入信号并产生耦合的N-NARY输出信号（V0-V3），其另外耦合到共享逻辑树电路。本发明使用包括2个N-NARY信号中的1个，3个N-NARY信号中的1个，4个N-NARY信号中的1个（A0-A3，B0-B3），8个N-NARY个信号中的1个，以及一般N N-NARY信号1。本发明评估包括AND / NAND，OR / NOR或异或/等效函数的任何给定函数。

5. 发明申请

WO01024367A1 NOISE TOLERANT CONDUCTANCE-BASED LOGIC GATE AND METHODS OF OPERATION AND MANUFACTURING THEREOF 审中-公开
标题翻译：基于噪声容限的逻辑门及其操作和制造方法
公开(公告)号：WO01024367A1
公开(公告)日：2001-04-05
申请号：PCT/US2000/025945
申请日：2000-09-21
IPC分类号： G06F7/50 , G06F7/501 , G06F7/52 , H03K19/08
CPC分类号： G06F7/52 , G06F7/5013 , G06F2207/4818 , H03K19/0813
摘要： A logic gate, an adder and methods of operating and manufacturing the same. In one embodiment, the logic gate includes: (1) a summer (140), having at least two single-bit inputs (Vi, Vi+1) and a noise-suppression input (V1) with corresponding conductances representing discrete weights, that generates a weighted sum of input binary digits presented at the at least two single-bit inputs and the noise-suppression input and (2) a quantizer (150), coupled to the summer (140), that generates an output binary digit at a binary output thereof (130) that is a function of the weighted sum, the noise-suppression input (V1) increasing a noise tolerance of the logic gate.
摘要翻译：逻辑门，加法器和操作和制造方法。在一个实施例中，逻辑门包括：（1）具有至少两个单位输入（Vi，Vi + 1）和具有表示离散权重的对应电导的噪声抑制输入（V1））的加法器（140），产生在所述至少两个单位输入和噪声抑制输入处呈现的输入二进制数字的加权和，以及耦合到所述加法器（140）的量化器（150），所述量化器（150）在作为加权和的函数的二进制输出（130），噪声抑制输入（V1）增加逻辑门的噪声容限。

6. 发明申请

WO1984002238A1 CLOCK DRIVER CIRCUIT 审中-公开
标题翻译：时钟驱动电路
公开(公告)号：WO1984002238A1
公开(公告)日：1984-06-07
申请号：PCT/US1983001571
申请日：1983-10-06
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , MOENCH, Jerry, Dale
IPC分类号： H03K19/08
CPC分类号： H03K19/01735
摘要： A clock driver circuit (40) advantageously uses natural transistors (41) to couple a signal to a bootstrap node (54) in a source-follower configuration in a 5 volt only system. A bootstrap circuit (40) with a natural transistor (51) output driver (44) has one input coupled to the bootstrap node (54) and a second input for receiving a delayed signal. The delayed signal is received from a delay circuit (43) which has an input for detecting a rise in voltage on the bootsrap node (54).
摘要翻译：时钟驱动器电路（40）有利地使用天然晶体管（41）将信号耦合到仅在5伏系统中的源极跟随器配置中的引导节点（54）。具有自然晶体管（51）输出驱动器（44）的自举电路（40）具有耦合到自举节点（54）的一个输入端和用于接收延迟信号的第二输入端。延迟信号从延迟电路（43）接收，延迟电路具有用于检测引导器节点（54）上的电压升高的输入。

7. 发明申请

WO2023013427A1 レベルシフタ、半導体装置、スイッチング電源、発光装置审中-公开
公开(公告)号：WO2023013427A1
公开(公告)日：2023-02-09
申请号：PCT/JP2022/028308
申请日：2022-07-21
申请人：ローム株式会社
发明人：青木　啓 , ▲高▼木　涼
IPC分类号： H03K19/0175 , H03K19/08 , H02M3/155
摘要：レベルシフタ２０は、第１出力端及び第２出力端からそれぞれ第１出力電流Ｉ１及び第２出力電流Ｉ２を出力するように構成された電流出力アンプＡ０と、電流出力アンプＡ０の反転入力端（－）及び第１出力端と接地電位の印加端（ＧＮＤＩＮ）との間に接続されるように構成された第１抵抗Ａ１と、電流出力アンプＡ０の第２出力端と接地電位よりも低い負電位の印加端（ＳＩＮＮ）との間に接続されるように構成された第２抵抗Ａ２を有し、接地電位を基準とした第１アナログ信号ＶＤＣＤ１を電流出力アンプＡ０の非反転入力端（＋）で受け付け、負電位を基準とした第２アナログ信号ＶＤＣＤ２を第２抵抗Ａ２の一端から出力する。

8. 发明申请

WO2021176974A1 INVERTER BASED ON ELECTRON INTERFERENCE 审中-公开
公开(公告)号：WO2021176974A1
公开(公告)日：2021-09-10
申请号：PCT/JP2021/004857
申请日：2021-02-02
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： TEO, Koon Hoo , CHOWDHURY, Nadim
IPC分类号： H01L29/06 , H01L29/423 , H01L29/778 , H01L29/20 , B82Y10/00 , G06F7/38 , G06N10/00 , H03K19/08
摘要： Semiconductor device includes at least three arms. A channel from the first and second arms extends to a channel of the third arm. When a current due to an application of a first voltage is flowing from the first arm to the second arm, a flow of ballistic electrons is generated from the channel of the first and second arms to the channel of the third arm. A fin structure is located in the third arm and includes a gate over the fin structure. The gate is controlled using a second voltage. The fin structure is formed as to induce an energy-field structure that shifts by an amount of the second voltage to control an opening of the gate that the flow of ballistic electrons pass through, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then interference.

9. 发明申请

WO2019006138A1 GATE CONTROL CIRCUIT FOR A TRISTATE OUTPUT BUFFER 审中-公开
公开(公告)号：WO2019006138A1
公开(公告)日：2019-01-03
申请号：PCT/US2018/040045
申请日：2018-06-28
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： GRAVES, Christopher, Michael
IPC分类号： H03K19/0944 , H03K19/08
摘要： A gate control circuit (300 A) for a tri state output buffer operating in a first voltage domain includes a pull-up circuit (304 A) coupled between an upper rail (V CCB ) and a first gate control signal (V p ), a pull-down circuit (306 A) coupled between a lower rail (ground) and a second gate control signal (V N ), and a gate isolation switch (302A) coupled between the first gate control signal (V p ) and the second gate control signal (V N ). The gate isolation switch (302 A) includes a PMOS transistor coupled in parallel with an NMOS transistor. The NMOS transistor is controlled by a first enable signal (EN 1 ), and the PMOS transistor is controlled by a second enable signal (EN 2 ).

10. 发明申请

WO2019002761A1 PROCEDE DE CONTROLE D'UN DISPOSITIF QUANTIQUE A QUBIT DE SPIN 审中-公开
公开(公告)号：WO2019002761A1
公开(公告)日：2019-01-03
申请号：PCT/FR2018/051569
申请日：2018-06-27
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： BOURDET, Léo , HUTIN, Louis , NIQUET, Yann-Michel , VINET, Maud
IPC分类号： H01L43/00 , B82Y10/00 , G06N99/00 , H01L29/66 , H03K19/08
摘要： Procédé de contrôle d'un dispositif quantique (100) à qubit de spin comportant: -une portion semi-conductrice(102); -une couche diélectrique (104) recouverte par la portion semi- conductrice; -une grille avant (108) recouvrant partiellement une arrête supérieure (113) de la portion semi-conductrice; -une grille arrière; dans lequel, lors d'une manipulation d'un état du spin : -l'exposition du dispositif à un champ magnétique B de valeur telle que g.µ B .B > min(Δ(Vbg)), et -l'application, sur la grille arrière, d'un potentiel électrique Vbg de valeur telle que Δ(Vbg) B .B +2|M SO |, et l'application, sur la grille avant, d'un potentiel de confinement et d'un signal électrique RF déclenchant un changement d'état du spin, avec g correspondant au facteur de Landé, µ B correspondant au magnéton de Bohr, Δ correspondant à l'écart d'énergie inter-vallée dans la portion semi- conductrice, et M SO correspondant au couplage spin-orbite inter-vallées.

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