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1. 发明申请

WO2022267051A1 导电过孔的制备方法、导电过孔及无源器件审中-公开
公开(公告)号：WO2022267051A1
公开(公告)日：2022-12-29
申请号：PCT/CN2021/102525
申请日：2021-06-25
申请人：京东方科技集团股份有限公司
发明人：王熙元 , 曲峰
IPC分类号： H01L49/02 , H01L27/01 , H03H1/00 , H03H3/00
摘要：本公开提供一种导电过孔的制备方法，属于电子元件技术领域。本公开的导电过孔的制备方法，其包括：提供一介质层，并在所述介质层上形成在其厚度方向上贯穿的连接过孔；所述介质层包括在其厚度方向上相对设置的第一表面和第二表面；在所述连接过孔内形成连接电极，在所述第一表面形成第一引出电极，在所述第二表面形成第二引出电极；其中，所述连接电极至少覆盖所述连接过孔的内壁，且所述第一引出电极和所述第二引出电极均与所述连接电极电连接。

2. 发明申请

WO2021191860A1 CONTACT STRUCTURES IN RC-NETWORK COMPONENTS 审中-公开
公开(公告)号：WO2021191860A1
公开(公告)日：2021-09-30
申请号：PCT/IB2021/052529
申请日：2021-03-26
申请人： MURATA MANUFACTURING CO., LTD.
发明人： YAMAGUCHI, Yohei , MURASE, Yasuhiro , BOUVIER, Stéphane
IPC分类号： H01L27/01 , H01L27/06 , H01L49/02 , H01L29/94 , H01L27/016 , H01L27/0682 , H01L28/20 , H01L29/945
摘要： RC-network components (101) comprise a substrate (102) provided, at a surface on one side (102a) thereof, with a capacitor having a thin-film top electrode portion (107). The low ohmic semiconductor substrate (102) is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate (109), spaced from the thin-film top electrode portion (107) by an insulating layer (110), and a set of one or more bridging contacts (108) passing through openings (111) in the insulating layer (110). The bridging contacts electrically interconnect the thin-film top electrode portion (107) and the contact plate (109). Different resistance values can be set by appropriate selection of the number of bridging contacts (8). The openings (111) are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts (8) have an elongated cross-sectional shape.

3. 发明申请

WO2020190467A1 THIN-FILM RESISTORS WITH FLEXIBLE TERMINAL PLACEMENT FOR AREA SAVING 审中-公开
公开(公告)号：WO2020190467A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/019841
申请日：2020-02-26
申请人： QUALCOMM INCORPORATED
发明人： CHINTARLAPALLI REDDY, Harikrishna , LOKE, Alvin Leng Sun
IPC分类号： H01L27/01 , H01L49/02 , H01C1/14 , H01L27/08
摘要： An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance.

4. 发明申请

WO2018095824A1 INTEGRATED ELECTRONIC COMPONENT SUITABLE FOR BROADBAND BIASING 审中-公开
公开(公告)号：WO2018095824A1
公开(公告)日：2018-05-31
申请号：PCT/EP2017/079668
申请日：2017-11-17
申请人： MURATA INTEGRATED PASSIVE SOLUTIONS
发明人： BOUVIER, Stéphane , TENAILLEAU, Jean-René
IPC分类号： H01L49/02 , H01F5/00 , H01F17/00 , H01F27/28 , H01L23/522 , H01L23/64 , H01L27/01 , H01L27/06
摘要： An integrated electronic component (10) suitable for broadband biasing comprises a monolithic substrate (1), a capacitor structure arranged in a trench (3) network which extends into the substrate, and a continuous track (8) of an electrically conducting material arranged in a crater (CR) which is formed in the substrate. The continuous track has one or several turns which have decreasing turn sections, and which are supported by a slanted peripheral wall (CRW) of the crater for forming an inductor. Manufacturing and mounting costs of the component are reduced and reproducibility for mass production of such components is improved. The components may be suitable for mounting on printed circuit boards (100).

5. 发明申请

WO2015083160A3 PROCESS FOR CONTROLLING WETTABILITY FEATURES 审中-公开
标题翻译：控制湿度特性的方法
公开(公告)号：WO2015083160A3
公开(公告)日：2015-10-08
申请号：PCT/IL2014051048
申请日：2014-12-02
申请人： CLEARJET LTD
发明人： GROUCHKO MICHAEL , MAGDASSI SHLOMO
IPC分类号： C09D11/52 , C09D11/033 , C23C4/18 , C23C26/00 , H01G9/20 , H01H49/00 , H01L27/01 , H01L27/28 , H01L33/42 , H01L51/00 , H05K1/09 , H05K3/12 , H05K3/24 , H05K3/46
CPC分类号： H05K3/1208 , C09D11/10 , C09D11/322 , C09D11/36 , C09D11/52 , C23C24/085 , H01L51/0005 , H01L51/0007 , H05K1/092 , H05K1/095 , H05K1/097 , H05K1/16 , H05K3/105 , H05K3/12 , H05K3/125 , H05K3/1283 , H05K3/227 , H05K3/245 , H05K3/4685 , H05K2201/0257 , H05K2201/026 , H05K2201/0323 , H05K2201/0329 , H05K2201/0338 , H05K2201/035 , H05K2201/0391 , H05K2201/09272 , H05K2201/09281 , H05K2201/09681 , H05K2201/09736 , H05K2201/098 , H05K2201/10053 , H05K2201/10106 , H05K2201/10121 , H05K2201/10128 , H05K2201/10143 , H05K2201/10151 , H05K2201/10166 , H05K2201/10174 , H05K2203/013 , H05K2203/0545 , H05K2203/0783 , H05K2203/081 , H05K2203/092 , H05K2203/095 , H05K2203/1105 , H05K2203/111 , H05K2203/1173 , H05K2203/1476 , H05K2203/1492 , H05K2203/173 , Y02E10/542 , Y02E10/549
摘要： The invention provides a process of forming a continuous pattern on a surface composed of two or more surface regions, each of the regions being of a different surface energy, the process utilizing a novel ink formulation for printing on such multi-region surfaces.
摘要翻译：本发明提供了一种在由两个或更多个表面区域组成的表面上形成连续图案的方法，每个区域具有不同的表面能，该方法利用新的油墨配方在这种多区域表面上印刷。

6. 发明申请

WO2015142591A1 FACE-UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：在半导体封装中与焊接球连接的面向基板集成
公开(公告)号：WO2015142591A1
公开(公告)日：2015-09-24
申请号：PCT/US2015/020021
申请日：2015-03-11
申请人： QUALCOMM INCORPORATED
发明人： KIM, Daeik Daniel , KIM, Jonghae , ZUO, Chengjie , YUN, Changhan Hobie , VELEZ, Mario Francisco , MIKULKA, Robert Paul
IPC分类号： H05K1/02 , H05K1/14 , H05K3/36 , H01L23/48 , H01L27/01 , H01L23/538 , H01L23/64 , H05K3/34 , H05K1/16
CPC分类号： H05K3/303 , H01L23/48 , H01L23/5385 , H01L23/645 , H01L2924/0002 , H01L2924/19101 , H05K1/0243 , H05K1/0306 , H05K1/111 , H05K1/141 , H05K1/144 , H05K1/165 , H05K1/18 , H05K3/3436 , H05K3/368 , H05K3/4007 , H05K3/4015 , H05K2201/1003 , H05K2201/10477 , H05K2201/10719 , H05K2201/10734 , H05K2201/10977 , H05K2203/041 , H05K2203/1316 , Y10T29/4902 , Y10T29/49126 , Y10T29/4913 , Y10T29/49146 , H01L2924/00
摘要： FACE-UP SUBSTRATE INTEGRATION WITH SOLDER BALL CONNECTION IN SEMICONDUCTOR PACKAGE Systems and methods relate to a semiconductor package 200 comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component 204 and a first set of one or more package pads 203 formed on a face of a glass substrate 202. The semiconductor package also includes a second or laminate substrate 207 with a second set of one or more package pads 205 formed on a face of the second or laminate substrate. Solder balls 206 are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) 208 can be coupled to a bottom side of the second or laminate substrate.
摘要翻译：具有半导体封装中的焊接球连接的正面基板集成系统和方法涉及包括第一基板或2D无源玻璃（POG）结构的半导体封装200，其具有无源元件204和第一组一个或多个形成在玻璃基板202的表面上的封装焊盘203.半导体封装还包括具有形成在第二或层叠基板的表面上的第二组一个或多个封装焊盘205的第二或层压基板207。焊球206被落下，被配置为使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一衬底或2D POG结构朝上放置在第二或层压基板。印刷电路板（PCB）208可以联接到第二或层压基板的底侧。

7. 发明申请

WO2015080770A1 HIGH QUALITY FACTOR INDUCTIVE AND CAPACITIVE CIRCUIT STRUCTURE 审中-公开
标题翻译：高品质因素电感和电容电路结构
公开(公告)号：WO2015080770A1
公开(公告)日：2015-06-04
申请号：PCT/US2014/046021
申请日：2014-07-09
申请人： XILINX, INC.
发明人： JING, Jing , WU, Shuxian , WU, Zhaoyin, D.
IPC分类号： H01L27/01 , H01L23/522 , H01L49/02 , H05K1/16 , H03H7/01
CPC分类号： H03H7/0115 , H01L23/5223 , H01L23/5227 , H01L27/016 , H01L28/10 , H01L28/60 , H01L28/88 , H01L2924/0002 , H03H5/02 , H03H7/0138 , H05K1/16 , Y10T29/49117 , H01L2924/00
摘要： A circuit includes a first finger capacitor (100) having a first bus line (110) coupled to a first plurality of finger elements (120) and a second bus line (105) coupled to a second plurality of finger elements (115). The first bus line is parallel to the second bus line. The circuit further includes an inductor (500) having a first leg (125, 515) oriented perpendicular to the first bus line and the second bus line. The first leg of the inductor is coupled to a center (135) of the first bus line. Related methods are also disclosed.
摘要翻译：电路包括具有耦合到第一多个指状元件（120）的第一总线线路（110）和耦合到第二多个指状元件（115）的第二总线线路（105））的第一手指电容器（100）。第一条总线与第二条总线平行。电路还包括具有垂直于第一总线和第二总线定向的第一支脚（125,515）的电感器（500）。电感器的第一支路耦合到第一总线的中心（135）。还公开了相关方法。

8. 发明申请

WO2014048639A1 VERFAHREN ZUM HERSTELLEN EINES PASSIVEN ELEKTRONISCHEN BAUELEMENTS, VERFAHREN ZUM HERSTELLEN EINER OPTOELEKTRONISCHEN BAUGRUPPE UND PASSIVES ELEKTRONISCHES BAUELEMENT 审中-公开
标题翻译：一种用于生产无源电子元件，方法制造光电组件和无源电子元件
公开(公告)号：WO2014048639A1
公开(公告)日：2014-04-03
申请号：PCT/EP2013/067348
申请日：2013-08-20
申请人： OSRAM OPTO SEMICONDUCTORS GMBH
发明人： INGLE, Andrew
IPC分类号： H01L27/01 , H01L23/522 , H01L49/02 , H01G4/33 , H01G4/005
CPC分类号： H01L27/3225 , H01G4/005 , H01G4/33 , H01L27/016 , H01L27/0682 , H01L28/20 , H01L28/40 , H01L28/60 , H01L51/56
摘要： In verschiedenen Ausführungsbeispielen wird ein Verfahren zum Herstellen eines passiven elektronischen Bauelements bereitgestellt. Dabei wird eine erste elektrisch leitfähige Schicht (12) auf einem Substrat (10) ausgebildet. Eine zweite elektrisch leitfähige Schicht (14) wird auf der ersten elektrisch leitfähigen Schicht (12) ausgebildet. In der ersten und zweiten elektrisch leitfähigen Schicht (12, 14) wird ein erster Graben (24) so ausgebildet, dass das Substrat (10) in dem ersten Graben (24) frei gelegt ist, wobei der erste Graben (24) einen ersten Kontaktbereich (16) von einem zweiten Kontaktbereich (18) abgrenzt. Ein Dielektrikum (28) wird derart strukturiert auf die zweite elektrisch leitfähige Schicht (14) in dem ersten Kontaktbereich (16) und zumindest teilweise auf das Substrat (10) in dem ersten Graben (24) aufgebracht, dass das Dielektrikum (28) den ersten Kontaktbereich (16) gegenüber dem zweiten Kontaktbereich (18) elektrisch isoliert. Eine elektrisch leitfähige Elektrodenschicht (38) wird über dem ersten Kontaktbereich (16) auf das Dielektrikum (28) und auf den zweiten Kontaktbereich (18) strukturiert aufgebracht.
摘要翻译：在各种实施方案中，提供了一种制造无源电子元件的方法。形成在基板（10）上形成第一导电层（12）。第二导电层（14）形成在第一导电层（12）上。在形成为使得在所述第一沟槽中的所述衬底（10）（24）被覆盖在第一和第二导电层（12,14），一个第一沟槽（24），其中，所述第一沟槽（24）包括第一接触部分（16）从第二接触区域（18）分隔开。电介质（28）在第一接触区域（16）中的第二导电层（14）上这样的方式被构造，并且至少部分（10），以在所述第一沟槽（24）在基板施加使得电介质（28），所述第一第二接触区域（18）相对的接触区域（16）电绝缘。过在电介质（28）的第一接触区域（16）和所述第二接触区域（18），被构造的方式的导电电极层（38）。

9. 发明申请

WO2007127925B1 TECHNIQUE FOR STABLE PROCESSING OF THIN/FRAGILE SUBSTRATES 审中-公开
标题翻译：用于稳定处理薄/弱基材的技术
公开(公告)号：WO2007127925B1
公开(公告)日：2008-12-18
申请号：PCT/US2007067640
申请日：2007-04-27
申请人： ICEMOS TECHNOLOGY CORP , WILSON ROBIN , BROGAN CONOR , GRIFFIN HUGH J , MACNAMARA CORMAC
发明人： WILSON ROBIN , BROGAN CONOR , GRIFFIN HUGH J , MACNAMARA CORMAC
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/78
摘要： A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.
摘要翻译：绝缘体上半导体（SOI）晶片包括具有彼此相对的第一和第二主表面的半导体衬底。电介质层设置在半导体衬底的第一主表面的至少一部分上。器件层具有第一主表面和第二主表面。器件层的第二主表面设置在与半导体衬底相对的电介质层的表面上。在装置层的第一主表面上限定多个预期的模具区域。多个预期的模具区域彼此分离。多个裸片存取沟槽从第二主表面形成在半导体衬底中。多个管芯存取沟槽中的每一个通常设置在多个预期管芯区域中的至少一个相应的一个的下方。

10. 发明申请

WO2007127503A3 STRUCTURE AND METHOD FOR MOSFET GATE ELECTRODE LANDING PAD 审中-公开
公开(公告)号：WO2007127503A3
公开(公告)日：2007-11-08
申请号：PCT/US2007/060564
申请日：2007-01-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： CLEVENGER, Lawrence, A. , DALTON, Timothy, J. , HSU, Louis, C. , RADENS, Carl , WONG, Kwong-Hon , YANG, Chih-chao
IPC分类号： H01L27/01
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

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