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1. 发明申请

WO2022169401A1 METHOD AND SYSTEM FOR PERFORMING A DIGITAL PROCESS 审中-公开
公开(公告)号：WO2022169401A1
公开(公告)日：2022-08-11
申请号：PCT/SE2022/050127
申请日：2022-02-04
申请人： EQT AB
发明人： CASELLA, Pietro Michele da Silveira de Oliveira
IPC分类号： G06F16/23 , G06Q20/08 , G06Q30/06 , G06Q40/00 , G06F9/44 , G06F9/46 , G06F13/12 , G06F15/16 , G06F21/31 , G06N20/00 , G06Q10/00
摘要： Method for performing a digital process (P). In the method, a central system initiates the process with a defined set of at least a second activity (A2) to be performed by a second, autonomous peripheral system (220). Further, the central system requests said second peripheral system to perform said second activity, the second peripheral system performs said second activity, and a resulting second piece of information (I2) is made available to said central system. Then, the central system updates a process status based on the second piece of information. The invention is characterised in that a second request (R2) comprises a second identifier (ID2), in that said second piece of information is made available to the central system via a digital work product (WP) output by the second peripheral system, in that the central system collects said work product; finds an anchor piece of information or pattern (I2') in the work product and identifies said second piece of information in said work product using said anchor. Furthermore, the finding is performed by a trained machine learning model. A successful finding results in a fully automatic extraction of the second piece of information. An unsuccessful finding results in that an interpretation is performed at least partly based on manual input, and the machine learning model is updated. The invention also relates to a system.

2. 发明申请

WO2022169400A1 METHOD AND SYSTEM FOR PERFORMING A DIGITAL PROCESS 审中-公开
公开(公告)号：WO2022169400A1
公开(公告)日：2022-08-11
申请号：PCT/SE2022/050126
申请日：2022-02-04
申请人： EQT AB
发明人： CASELLA, Pietro Michele da Silveira de Oliveira
IPC分类号： G06F16/23 , G06Q20/08 , G06Q30/06 , G06Q40/00 , G06F9/44 , G06F9/46 , G06F13/12 , G06F15/16 , G06F21/31 , G06N20/00 , G06Q10/00
摘要： Method and system for performing a digital process (P). A central system initiates the pro-cess with a defined set of at least a first activity (A1) to be performed by a first autonomous peripheral system (210) and at least a second activity (A2) to be performed by a second, different, autonomous peripheral system (220). The central system requests said first/sec-ond peripheral systems to perform said activities. Said systems perform said activities. Re-sulting first/second pieces of information (I1) and (I2) are made available to said central system, which updates a process status based on both pieces of information. The invention is characterised in that a second request (R2) comprises a second identifier (ID2), said second piece of information is made available to the central system via a digital work product (WP) output by the second peripheral system. The work product includes an anchor piece of information or pattern (I2') that identifies said second piece of information.

3. 发明申请

WO2022103812A1 AUTOMATIC DISCOVERY OF RELATIONSHIPS AMONG EQUIPMENT THROUGH AUTOMATED CYCLING AND OBSERVATION 审中-公开
公开(公告)号：WO2022103812A1
公开(公告)日：2022-05-19
申请号：PCT/US2021/058748
申请日：2021-11-10
申请人： MAPPED INC.
发明人： COOLEY, Shaun , DE CASTRO, Jose , KOH, Jason
IPC分类号： G05B19/42 , G06F13/12 , G06F17/30
摘要： Described are platforms, systems, and methods to discover relationships among equipment in automated industrial or commercial environments by cycling each individual piece of equipment while observing sensors in all other equipment in order to measure how each part reacts to each other part. The platforms, systems, and methods identify a plurality of data sources associated with an automation environment; issue one or more commands to cycle a current data source in the a plurality of data sources; monitor the automation environment for events or state changes in the data sources; detect one or more events or one or more state changes in one or more other data sources in the a plurality of data sources; and determine one or more relationships between the current data source and the one or more other data sources.

4. 发明申请

WO2021162762A1 PLATFORM CONTROLLER HUB (PCH) CHIPSETS IN PLATFORMS AS EXTENDED IO EXPANDER(S) 审中-公开
公开(公告)号：WO2021162762A1
公开(公告)日：2021-08-19
申请号：PCT/US2020/060416
申请日：2020-11-13
申请人： SRIVASTAVA, Amit K. , SHUSHTARIAN, Majid , ENAMANDRAM, Anand K. , HAVICAN, Jared W. , PIHLMAN, Jeffrey A. , KARAS, Michael J. , KRITHIVAS, Ramamurthy , WATNIK, Christine
发明人： SRIVASTAVA, Amit K. , SHUSHTARIAN, Majid , HAVICAN, Jared W. , PIHLMAN, Jeffrey A. , KARAS, Michael J. , KRITHIVAS, Ramamurthy , WATNIK, Christine
IPC分类号： G06F13/12 , G06F9/4401
摘要： Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH.

5. 发明申请

WO2021029871A1 THREAD MAPPING 审中-公开
公开(公告)号：WO2021029871A1
公开(公告)日：2021-02-18
申请号：PCT/US2019/046210
申请日：2019-08-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： DALTON, Christopher Ian , VILLATEL, Maugan , BELGARRIC, Pierre
IPC分类号： G06F13/12 , G06F11/07 , G06F9/22
摘要： There is provided a method for thread allocation in a multi-processor computing system. The method includes determining whether a thread for execution has a security requirement. The thread is allocated to one of a first processing unit or a second processing unit based on the determination. The thread is allocated for execution by the first processing unit based on the thread having the security requirement.

6. 发明申请

WO2020046179A1 ВИДЕОИНТЕРФЕЙС ТРАНСПОРТНОГО СРЕДСТВА 审中-公开
公开(公告)号：WO2020046179A1
公开(公告)日：2020-03-05
申请号：PCT/RU2019/050136
申请日：2019-08-22
申请人： ОБЩЕСТВО С ОГРАНИЧЕННОЙ ОТВЕТСТВЕННОСТЬЮ "КИБЕРКАР МОТОР РУС"
发明人： ПАРХОМЕНКО, Виталий Вячеславович
IPC分类号： B60R25/00 , G06F3/00 , G06F13/12 , G06F13/38
摘要： Изобретение относится к устройствам для передачи информации, ее визуализации на приборной панели транспортного средства в форме видеосигнала, а также для подключения к штатным системам транспортного средства устройств, установка которых изначально не предусмотрена конфигурацией автомобиля. У стройство включает в себя установленную в корпус одну или несколько печатных плат с размещенными на них устройством ввода информации (1), модулем беспроводного подключения Wi-Fi и Bluetooth (2), модулем громкой связи (3), модулем связи 3G/4G/GSM (4), модулем приема и обработки данных геолокации (5), модулем подключения периферийных устройств по USB (6), модулем подключения SD-карт (7), модулем управления устройствами через инфракрасный порт (8), модулем коммутации и преобразования видеосигнала (9), модулем взаимодействия с дополнительными устройствами (10), модулем подключения к шине данных (11), модулем подключения сенсорного управления (12), модулем обработки видеосигнала форматов RGBVDigital RGBVLVDS (13), модулем установки навигационной системы (13а), модулем обработки видеосигнала формата CVBS и стерео-аудиосигнала (14), модулем обработки видеосигнала формата HDMI (15), модулем программирования и обновления программного обеспечения (16), модулем коммутации и преобразования аудиосигнала с выводом для подключения динамика (17), центральным модулем управления (18).

7. 发明申请

WO2020023716A1 DATA SYSTEM ON A MODULE (DSoM) FOR CONNECTING COMPUTING DEVICES AND CLOUD-BASED SERVICES 审中-公开
公开(公告)号：WO2020023716A1
公开(公告)日：2020-01-30
申请号：PCT/US2019/043383
申请日：2019-07-25
申请人： BLUES INC.
发明人： OZZIE, Raymond Edward
IPC分类号： G06F13/00 , G06F13/12 , G06F13/42 , H04L12/00 , H04L12/433 , H04W84/00 , H04W84/02 , H04W84/04 , H04W88/14 , H04W88/18
摘要： A communication hub configured to be communicatively coupled to a communication device (e.g., a data system on a module (DSoM) / a Data System in a Package (DSiP)) and a cloud-based service is provided. The communication hub may be configured to organize the communication devices into one or more communication device groups, wherein the communication devices are communicatively coupled to one or more computing devices. The communication hub may be configured to associate one or more routes with the communication device groups, wherein the routes are configured to route data objects between the communication devices and the cloud-based service. The communication hub may be configured to asynchronously, with respect to the computing devices, route the data objects between the communication devices and the cloud-based service. Embodiments of the present disclosure may provide a distributed replicated spatiotemporal database packaged on a communication device and integrated with an internet-based secure communication hub

8. 发明申请

WO2019207586A1 MULTIPLE PROCESSOR COMPUTING DEVICE WITH CONFIGURABLE ELECTRICAL CONNECTIVITY TO PERIPHERALS 审中-公开
公开(公告)号：WO2019207586A1
公开(公告)日：2019-10-31
申请号：PCT/IL2019/050462
申请日：2019-04-24
申请人： TECHNION RESEARCH & DEVELOPMENT FOUNDATION LIMITED
发明人： TSAFRIR, Dan , SMOLYAR, Igor
IPC分类号： G06F13/16 , G06F13/12
摘要： A computing device, comprising at least one peripheral computing component, electrically connected to each of a plurality of hardware processors; wherein at least one of the plurality of hardware processors is adapted to executing a code for: configuring the at least one peripheral computing component to access at least one first memory location in a first memory component electrically coupled with a first hardware processor of the plurality of hardware processors via a first electrical connection between the peripheral computing component and the first hardware processor; and configuring the at least one peripheral computing component to access at least one second memory location in a second memory component electrically coupled with a second hardware processor of the plurality of hardware processors via a second electrical connection between the peripheral computing component and the second hardware processor; and wherein the first hardware processor is not the second hardware processor.

9. 发明申请

WO2019200097A1 COMMUNICATION BETWEEN AN IMAGE FORMING DEVICE AND A REPLACEABLE SUPPLY ITEM 审中-公开
公开(公告)号：WO2019200097A1
公开(公告)日：2019-10-17
申请号：PCT/US2019/026986
申请日：2019-04-11
申请人： LEXMARK INTERNATIONAL, INC.
发明人： FOLEY, Nathan, Wayne , WILLIAMS, Jennifer, Topmiller , WOODS, Gregory, Scott , MOORE, Jimmy, Daniel
IPC分类号： H04N1/32 , H04N1/23 , G03G15/08 , G06F13/12 , G06F13/42
摘要： A toner container installable in an image forming device having a controller according to one example embodiment includes a housing having a reservoir for storing toner. A chip is positioned on the housing and configured to receive a first write command from the controller of the image forming device. The chip is further configured to determine whether a transmission cycle bit of the first write command matches a transmission cycle bit of a second write command received by the chip from the controller of the image forming device previous to the first write command. The chip is further configured to resend to the controller of the image forming device a response to the second write command if the transmission cycle bit of the first write command matches the transmission cycle bit of the second write command.

10. 发明申请

WO2019191431A1 PROTOCOL LEVEL CONTROL FOR SYSTEM ON A CHIP (SoC) AGENT RESET AND POWER MANAGEMENT 审中-公开
公开(公告)号：WO2019191431A1
公开(公告)日：2019-10-03
申请号：PCT/US2019/024586
申请日：2019-03-28
申请人： PROVINO TECHNOLOGIES, INC.
发明人： DESAI, Shailendra , PEARCE, Mark , JAIN, Amit , BHATT, Rutul , PATEL, Jaymin
IPC分类号： G06F13/10 , G06F13/12 , G06F13/14
摘要： A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

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