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1. 发明申请

WO2021191527A1 PROCEDE DE FABRICATION D'UNE STRUCTURE EMPILEE 审中-公开
公开(公告)号：WO2021191527A1
公开(公告)日：2021-09-30
申请号：PCT/FR2021/050434
申请日：2021-03-16
申请人： SOITEC
发明人： GHYSELEN, Bruno , DARRAS, François-Xavier
IPC分类号： H01L21/762 , H01L21/187 , H01L21/76254 , H01L27/0688
摘要： L'invention concerne un procédé de fabrication d'une structure empilée comprenant un substrat receveur et un film superficiel, le procédé comprenant les étapes suivantes : a) la fourniture d'un substrat support et d'un substrat initial, chacun présentant une face avant et une face arrière, b) la formation d'un plan fragile enterré dans le substrat support ou dans le substrat initial, par implantation d'ions légers à travers la face avant de l'un ou l'autre desdits substrats, c) l'assemblage du substrat support et du substrat initial par leurs faces avant respectives, d) l'amincissement mécanique et/ou chimique du substrat initial par sa face arrière pour former un substrat donneur comprenant une couche donneuse issue du substrat initial et disposée sur le substrat support, et le plan fragile enterré présent dans le substrat support ou dans la couche donneuse, le substrat donneur présentant une face avant, du côté de la couche donneuse et une face arrière du côté du substrat support, e) la fourniture d'un substrat receveur présentant une face avant et une face arrière, f) l'assemblage du substrat donneur et du substrat receveur par leurs faces avant respectives, g) la séparation le long du plan fragile enterré, de manière à former la structure empilée comprenant le substrat receveur et le film superficiel incluant tout ou partie de la couche donneuse.

2. 发明申请

WO2020231545A1 PACKAGE STRUCTURE AND FABRICATION METHODS 审中-公开
公开(公告)号：WO2020231545A1
公开(公告)日：2020-11-19
申请号：PCT/US2020/026874
申请日：2020-04-06
申请人： APPLIED MATERIALS, INC.
发明人： CHEN, Han-Wen , VERHAVERBEKE, Steven , PARK, Giback , CELLERE, Giorgio , TONINI, Diego , DICAPRIO, Vincent , CHO, Kyuil
IPC分类号： H01L23/28 , H01L23/48 , H01L23/522 , H01L2021/60007 , H01L21/4846 , H01L21/486 , H01L21/4864 , H01L21/50 , H01L21/76802 , H01L2224/04105 , H01L2224/18 , H01L2224/73267 , H01L2224/92244 , H01L2225/1035 , H01L2225/107 , H01L23/13 , H01L23/147 , H01L23/15 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L23/49894 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/5389 , H01L23/66 , H01L25/0657 , H01L25/105 , H01L27/0688 , H01Q1/2283 , H01Q1/243 , H05K1/0243
摘要： The present disclosure relates to methods and apparatus for forming a thin- form -factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

3. 发明申请

WO2022240733A1 INVERTED CROSS-COUPLE FOR TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3DI 审中-公开
公开(公告)号：WO2022240733A1
公开(公告)日：2022-11-17
申请号：PCT/US2022/028301
申请日：2022-05-09
申请人： TOKYO ELECTRON LIMITED , TOKYO ELECTRON U.S. HOLDINGS, INC.
发明人： CHANEMOUGAME, Daniel , LIEBMANN, Lars , SMITH, Jeffrey , GUTWIN, Paul
IPC分类号： H01L21/822 , H01L21/8234 , H01L21/8238 , H01L23/528 , H01L27/06 , H01L27/088 , H01L29/423 , H01L29/786 , H01L21/8221 , H01L21/823807 , H01L21/823871 , H01L27/0688 , H01L27/092 , H01L27/0922 , H01L29/0665 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.

4. 发明申请

WO2022046482A2 FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS 审中-公开
公开(公告)号：WO2022046482A2
公开(公告)日：2022-03-03
申请号：PCT/US2021/046455
申请日：2021-08-18
申请人： MICRON TECHNOLOGY, INC.
发明人： KIRBY, Kyle K. , PAREKH, Kunal R.
IPC分类号： H01L23/485 , H01L27/11573 , H01L21/60 , H01L21/683 , H01L21/50 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L2221/68363 , H01L2221/68381 , H01L2224/02125 , H01L2224/02145 , H01L2224/0235 , H01L2224/02351 , H01L2224/02372 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05557 , H01L2224/05559 , H01L2224/05569 , H01L2224/05647 , H01L2224/08058 , H01L2224/08145 , H01L2224/09181 , H01L2224/13111 , H01L2224/80006 , H01L2224/80357 , H01L2224/80895 , H01L2224/9202 , H01L2225/06541 , H01L23/5384 , H01L23/5386 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/09 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/092 , H01L27/11582
摘要： Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

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