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1. 发明申请

WO2009006405A1 MULTI-INPUT MULTI-OUTPUT TIME ENCODING AND DECODING MACHINES 审中-公开
标题翻译：多输入多输出时间编码和解码机
公开(公告)号：WO2009006405A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/068790
申请日：2008-06-30
申请人： THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK , LAZAR, Aurel, A. , PNEVMATIKAKIS, Eftychios, A.
发明人： LAZAR, Aurel, A. , PNEVMATIKAKIS, Eftychios, A.
IPC分类号： H03M7/00
CPC分类号： H03M3/466 , G06N3/049 , H03M1/1205 , H03M1/125 , H03M1/50 , H03M1/662 , H03M1/82 , H03M3/43 , H03M3/504
摘要： Methods and systems for encoding and decoding signals using a Multi-input Multi- output Time Encoding Machine (TEM) and Time Decoding Machine are disclosed herein.
摘要翻译：本文公开了使用多输入多输出时间编码机（TEM）和时间解码机对信号进行编码和解码的方法和系统。

2. 发明申请

WO2008151137A2 REAL-TIME TIME ENCODING AND DECODING MACHINES 审中-公开
标题翻译：实时编码和解码机
公开(公告)号：WO2008151137A2
公开(公告)日：2008-12-11
申请号：PCT/US2008/065542
申请日：2008-06-02
申请人： THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK , LAZAR, Aurel, A. , SIMONYI, Erno, K. , TOTH, Laszlo, T.
发明人： LAZAR, Aurel, A. , SIMONYI, Erno, K. , TOTH, Laszlo, T.
IPC分类号： H03M1/02
CPC分类号： A61B5/0002 , A61B5/04012 , H03M1/125 , H03M1/50 , H03M1/82 , H03M3/432 , H03M3/502
摘要： Methods for decoding a signal encoded by a Time Encoding Machine (TEM) include defining a plurality of time-windows, each time- window corresponding to a portion of a TEM-encoded signal and made up of a plurality of trigger values, at least two of the time- windows overlapping, decoding each of the time-windows using a Time Decoding Machine (TDM) to generate a decoded time- window, and stitching the decoded time-windows together to generate a TEM-decoded signal.
摘要翻译：用于解码由时间编码机（TEM）编码的信号的方法包括定义多个时间窗口，每个时间窗口对应于TEM编码信号的一部分并由多个触发值组成，每个时间窗口至少两个的时间窗重叠，使用时间解码机（TDM）解码每个时间窗口以产生解码的时间窗口，并将解码的时间窗口拼接在一起以产生TEM解码的信号。

3. 发明申请

WO01056008A1 POINTING DEVICE WITH Z-AXIS FUNCTIONALITY AND REDUCED COMPONENT COUNT 审中-公开
标题翻译：具有Z轴功能和减少组件计数的指示装置
公开(公告)号：WO01056008A1
公开(公告)日：2001-08-02
申请号：PCT/US2001/002389
申请日：2001-01-24
IPC分类号： G05G9/047 , G06F1/32 , G06F3/038 , H02J7/00 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , G09G5/08
CPC分类号： G06F3/0383 , G05G9/047 , G05G2009/04777 , G06F1/3203 , G06F1/3237 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , Y02D10/128
摘要： Apparatus and method are disclosed for receiving human input by means of a pointing device, typically a strain gauge (72, 73, 74, 75). Three dimensions of input are received from a resistor bridge (1) by means of four contact points to the strain gauge (72, 73, 74, 75). A sequence of excitation signals is applied to the bridge (1) and a multiplexer (12) is employed to permit a signal processor (30) to sample sensor outputs. The apparatus processes the sampled outputs and determines the user inputs such as X and Y and Z values of the pointing device.
摘要翻译：公开的装置和方法用于通过指示装置（通常为应变仪（72,73,74,75））接收人的输入。输入的三个尺寸通过四个接触点从应变仪（72,73,74,75）从电阻桥（1）接收。激励信号的序列被施加到桥（1），并且使用多路复用器（12）来允许信号处理器（30）对传感器输出进行采样。该装置处理采样的输出并确定诸如指示装置的X和Y和Z值的用户输入。

4. 发明申请

WO2016027683A1 固体撮像素子および電子機器审中-公开
标题翻译：固态图像拾取元件和电子设备
公开(公告)号：WO2016027683A1
公开(公告)日：2016-02-25
申请号：PCT/JP2015/072322
申请日：2015-08-06
申请人：ソニー株式会社
发明人：阿比留　隆浩 , 久松　康秋 , 永田　忠史
IPC分类号： H04N5/378 , H03M1/56 , H03M1/66
CPC分类号： H04N5/378 , H03M1/123 , H03M1/1295 , H03M1/56 , H03M1/66 , H03M1/82
摘要：　本開示は、ゲイン遷移を高速に行うことができる固体撮像素子および電子機器に関する。ランプ生成回路は、必要なゲインの種類（例えば、低ゲインと高ゲインの２種類）に応じた数のサンプルホールド回路およびランプ生成用DACを備えている。そして、２つのサンプルホールド回路は、異なるゲインのゲインDAC出力電圧を個別に保持することができる。これにより、ランプ選択信号にて必要なゲイン電圧を保持したランプ生成用DACに切り替えることができる。本開示は、例えば、撮像装置に用いられるCMOS固体撮像素子に適用することができる。
摘要翻译：本公开内容涉及：可以高速执行增益转换的固态图像拾取元件; 和电子设备。本发明的斜坡发生电路设置有对应于必要增益种类的数量的采样保持电路和斜坡发生DA转换器（DAC）（例如，两种增益，即低增益和高收益）。两个采样保持电路可以分别保持不同增益的增益DAC输出电压。因此，通过斜坡选择信号使斜坡发生DAC的切换成为可能，所述斜坡发生DAC保持必要的增益电压。本公开可以应用于例如用于图像拾取装置中的CMOS固态图像拾取元件。

5. 发明申请

WO2013092876A1 CIRCUIT AND METHOD 审中-公开
标题翻译：电路和方法
公开(公告)号：WO2013092876A1
公开(公告)日：2013-06-27
申请号：PCT/EP2012/076405
申请日：2012-12-20
申请人： INTEL MOBILE COMMUNICATIONS GMBH , KLEPSER, Bernd-Ulrich , SCHOLZ, Markus , BOOS, Zdravko , MAYER, Thomas
发明人： KLEPSER, Bernd-Ulrich , SCHOLZ, Markus , BOOS, Zdravko , MAYER, Thomas
IPC分类号： H04L27/36 , H04L27/20
CPC分类号： H03M1/74 , H03M1/82 , H04L27/2003 , H04L27/361
摘要： Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.
摘要翻译：本发明的实施例产生具有数字 - 时间转换器的电路，其具有用于接收高频信号的高频输入端，用于接收第一数字信号的数字输入端和用于提供高频信号的高频输出端时间延迟版本的HF信号。此外，电路具有用于提供高频信号的振荡器装置，具有用于调节高频信号的频率的锁相环。数字 - 时间转换器被设计为基于在其数字输入处接收的第一数字信号按时间顺序延迟所接收的高频信号。

6. 发明申请

WO2012082140A1 APPARATUS AND METHOD FOR PROVIDING TIMING ADJUSTMENT OF INPUT SIGNAL 审中-公开
标题翻译：提供输入信号时序调整的装置和方法
公开(公告)号：WO2012082140A1
公开(公告)日：2012-06-21
申请号：PCT/US2010/061032
申请日：2010-12-17
申请人： AGILENT TECHNOLOGIES, INC. , ABRAMZON, Valentin
发明人： ABRAMZON, Valentin
IPC分类号： H03M1/66
CPC分类号： H03K5/06 , H03K5/133 , H03K5/14 , H03K2005/00026 , H03M1/682 , H03M1/82
摘要： An apparatus for providing time adjustment of an input signal includes a coarse timing digital-to-analog converter (DAC), a replica delay element and an interpolator. The coarse timing DAC has multiple delay settings for providing a coarse timing adjustment of the input signal, and outputs a first delayed signal by delaying the input signal by a first delay time corresponding to a selected setting of the multiple delay settings. The replica delay element receives the first delayed signal from the coarse timing DAC and outputs a second delayed signal by delaying the first delayed signal by a predetermined second delay time. The interpolator blends either the input signal and the first delayed signal or the first delayed signal and the second delayed signal for providing a fine timing adjustment of the input signal, and outputs a timing adjusted output signal including the coarse timing adjustment and the fine timing adjustment.
摘要翻译：用于提供输入信号的时间调整的装置包括粗略定时数模转换器（DAC），复制延迟元件和内插器。粗定时DAC具有多个延迟设置，用于提供输入信号的粗略定时调整，并且通过将输入信号延迟与对应于多个延迟设置的所选设置的第一延迟时间来输出第一延迟信号。复制延迟元件从粗定时DAC接收第一延迟信号，并通过将第一延迟信号延迟预定的第二延迟时间来输出第二延迟信号。内插器将输入信号和第一延迟信号或第一延迟信号和第二延迟信号混合，以提供输入信号的精细定时调整，并输出包括粗略定时调整和精细定时调整的定时调整输出信号。

7. 发明申请

WO2003034253A1 REDUCING OUTPUT CAPACITANCE OF DIGITAL-TO-TIME DOMAIN CONVERTER FOR VERY HIGH FREQUENCY DIGITAL WAVEFORM SYNTHESIS 审中-公开
标题翻译：降低非常高频数字波形合成的数字时域转换器的输出电容
公开(公告)号：WO2003034253A1
公开(公告)日：2003-04-24
申请号：PCT/US2002/033566
申请日：2002-10-17
申请人： INTEL CORPORATION
发明人： BAZES, Melvin
IPC分类号： H03M1/82
CPC分类号： H03M1/82
摘要： In one embodiment, N transmission gates having N outputs transfer one of N pattern inputs to a first output based on an active signals from N select signals. The N outputs are connected together to form the first output and has an output capacitance. An amplifier circuit having a gain is coupled to the N transmission gates at the first output to reduce the output capacitance by an amount approximately equal to the gain. The amplifier circuit generates an output signal.
摘要翻译：将XML文档转换为HTML文档的系统和方法，如HTML文档可追溯到原始的XML文档。收件人将转换的XML文档视为HTML文档，然后对HTML文档进行更改（160）。收件人所做的更改将被并入HTML文档中。

8. 发明申请

WO0156145A9 POWER-CONSERVING EXTERNAL CLOCK FOR USE WITH A CLOCK-DEPENDENT INTEGRATED CIRCUIT 审中-公开
标题翻译：电源保护外部时钟使用时钟相关集成电路
公开(公告)号：WO0156145A9
公开(公告)日：2002-10-31
申请号：PCT/US0102758
申请日：2001-01-27
申请人： SEMTECH NEW YORK CORP , MARTEN VICTOR
发明人： MARTEN VICTOR
IPC分类号： G05G9/047 , G06F1/32 , G06F3/038 , H02J7/00 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , H03B5/36
CPC分类号： G06F3/0383 , G05G9/047 , G05G2009/04777 , G06F1/3203 , G06F1/3237 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , Y02D10/128
摘要： The problem of undesired power consumption in an oscillator during "stop" periods of a device (35) is addressed by providing the oscillator in apparatus external to the device, the apparatus including a current sensor sensing current in a line between the apparatus and the device, the line (26) communicating an oscillator "clock" signal. If the device enters a "stop" state the current flow during certain half-cycles of the oscillation is relatively low compared to the current flow in the "no-stop" state. In response to a relatively low current, the apparatus halts oscillation (33). Later, when the device exits the "stop" state, current flow increases in the line, and the apparatus resumes oscillation, thereby resuming the communication of the clock signal to the device. Alternatively the apparatus monitors two oscillator lines by means of an XOR gate, powering down the oscillator when the XOR output goes low and restoring the oscillator when the XOR output goes high.
摘要翻译：通过在设备外部的设备中提供振荡器来解决在器件（35）的“停止”周期期间在振荡器中不期望的功率消耗的问题，所述设备包括感测电流在设备和设备之间的线路中的电流的电流传感器线（26）传送振荡器“时钟”信号。如果设备进入“停止”状态，则在“停止”状态下与当前流量相比，振荡的某些半周期期间的电流相对较低。响应于相对低的电流，该装置停止振荡（33）。之后，当设备退出“停止”状态时，电流在线路中增加，并且设备恢复振荡，从而恢复时钟信号到设备的通信。或者，该装置通过XOR门监控两个振荡器线路，当异或输出变为低电平时，对振荡器供电，并在XOR输出变为高电平时恢复振荡器。

9. 发明申请

WO01056163A1 INTENTIONALLY NON-MONOTONIC DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：意外的非单调数字到模拟转换器
公开(公告)号：WO01056163A1
公开(公告)日：2001-08-02
申请号：PCT/US2001/002390
申请日：2001-01-24
IPC分类号： G05G9/047 , G06F1/32 , G06F3/038 , H02J7/00 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , H03M1/12
CPC分类号： G06F3/0383 , G05G9/047 , G05G2009/04777 , G06F1/3203 , G06F1/3237 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , Y02D10/128
摘要： A digital-to-analog converter comprises capacitor stack (61, 62) , the common point of which is the output of the converter. Digitally controlled switches (66-70), which may be discrete outputs from a microcontroller, selectively apply first or second potentials to points in the capacitor stack, either directly (66, 70) or through resistors (63-65).
摘要翻译：数模转换器包括电容器堆叠（61,62），其公共点是转换器的输出。数字控制开关（66-70）可以是微控制器的离散输出，可以直接（66,70）或通过电阻（63-65）选择性地将第一或第二电位施加到电容器堆叠中的点。

10. 发明申请

WO01056145A1 POWER-CONSERVING EXTERNAL CLOCK FOR USE WITH A CLOCK-DEPENDENT INTEGRATED CIRCUIT 审中-公开
标题翻译：电源保护外部时钟使用时钟相关集成电路
公开(公告)号：WO01056145A1
公开(公告)日：2001-08-02
申请号：PCT/US2001/002758
申请日：2001-01-27
申请人： SEMTECH NEW YORK CORPORATION , MARTEN, Victor
发明人： MARTEN, Victor
IPC分类号： H03B5/36
CPC分类号： G06F3/0383 , G05G9/047 , G05G2009/04777 , G06F1/3203 , G06F1/3237 , H03K3/012 , H03L3/00 , H03M1/68 , H03M1/82 , Y02D10/128
摘要： The problem of undesired power consumption in an oscillator during "stop" periods of a device (35) is addressed by providing the oscillator in apparatus external to the device, the apparatus including a current sensor sensing current in a line between the apparatus and the device, the line (26) communicating an oscillator "clock" signal. If the device enters a "stop" state the current flow during certain half-cycles of the oscillation is relatively low compared to the current flow in the "no-stop" state. In response to a relatively low current, the apparatus halts oscillation (33). Later, when the device exits the "stop" state, current flow increases in the line, and the apparatus resumes oscillation, thereby resuming the communication of the clock signal to the device. Alternatively the apparatus monitors two oscillator lines by means of an XOR gate, powering down the oscillator when the XOR output goes low and restoring the oscillator when the XOR output goes high.
摘要翻译：通过在设备外部的设备中提供振荡器来解决振荡器在“停止”周期期间不期望的功率消耗的问题，该装置包括感测设备和设备之间的线路中的电流的电流传感器线（26）传送振荡器“时钟”信号。如果设备进入“停止”状态，则在“停止”状态下与当前流量相比，振荡的某些半周期期间的电流相对较低。响应于相对低的电流，该装置停止振荡（33）。之后，当设备退出“停止”状态时，电流在线路中增加，并且设备恢复振荡，从而恢复时钟信号到设备的通信。或者，该装置通过XOR门监控两个振荡器线路，当异或输出变为低电平时，对振荡器供电，并在XOR输出变为高电平时恢复振荡器。

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