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1. 发明申请

WO1982002793A1 SEMICONDUCTOR MEMORY REDUNDANT ELEMENT IDENTIFICATION CIRCUIT 审中-公开
标题翻译：半导体存储器冗余元件识别电路
公开(公告)号：WO1982002793A1
公开(公告)日：1982-08-19
申请号：PCT/US1981000137
申请日：1981-02-02
申请人： MOSTEK CORP , OTOOLE JAMES E , PROEBSTING ROBERT J
发明人： MOSTEK CORP
IPC分类号： G11C11/40
CPC分类号： G11C29/835 , G11C29/44
摘要： Test circuit (10) for a semiconductor memory. The semiconductor memory includes a redundant decoder (70) for receiving memory address signals (66, 68) which is connected to a redundant circuit element via a signal line (72). The redundant decoder (70) can be programmed in accordance with the address of a defective circuit element, such that when the decoder (70) is addressed by the memory address signals (66, 68) the decoder (70) selects a predetermined redundant circuit element. The test circuit (10) generates an output signal (14) indicating that the circuit element selected by the decoder (70) is a redundant circuit element. The output signal (14) is applied to an indicator circuit (16) which is enabled in a test mode by an abnormal condition detector (26). The output (18) of indicator circuit (16) is applied to an external pin (20).
摘要翻译：用于半导体存储器的测试电路（10）。半导体存储器包括用于经由信号线（72）连接到冗余电路元件的存储器地址信号（66,68）的冗余解码器（70）。可以根据故障电路元件的地址对冗余解码器（70）进行编程，使得当解码器（70）由存储器地址信号（66,68）寻址时，解码器（70）选择预定的冗余电路元件。测试电路（10）产生指示由解码器（70）选择的电路元件是冗余电路元件的输出信号（14）。输出信号（14）被施加到由异常状态检测器（26）在测试模式中使能的指示器电路（16）。指示电路（16）的输出（18）被施加到外部引脚（20）。

2. 发明申请

WO2015199700A1 POST PACKAGE REPAIR (PPR) DATA IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中的POST封装修复（PPR）数据
公开(公告)号：WO2015199700A1
公开(公告)日：2015-12-30
申请号：PCT/US2014/044354
申请日：2014-06-26
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： WARNES, Lidia , BENEDICT, Melvin, K. , WALTON, Andrew, C.
IPC分类号： G11C29/00 , G11C16/02
CPC分类号： G11C29/70 , G11C5/148 , G11C14/0018 , G11C29/44 , G11C29/808 , G11C29/835 , G11C2029/0409
摘要： Example implementations relate to post package repair (PPR) data in non- volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many of the plurality of repair units are available for performing post package repair (PPR) on the plurality of volatile memory devices, and how many PPRs have been performed on the memory module.
摘要翻译：示例实现涉及非易失性存储器中的后包修复（PPR）数据。在示例实现中，PPR数据可以存储在存储器模块上的非易失性存储器中。 PPR数据可以指示多个修复单元中有多少可用于在多个易失性存储器设备上执行后包修复（PPR），以及在存储器模块上执行了多少个PPR。

3. 发明申请

WO99030327A1 SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS EMPLOYING IT 审中-公开
标题翻译：半导体存储器件，半导体器件和使用其的电子设备
公开(公告)号：WO99030327A1
公开(公告)日：1999-06-17
申请号：PCT/JP1998/005585
申请日：1998-12-10
IPC分类号： G11C29/00
CPC分类号： G11C29/835
摘要： A redundant circuit outputting a redundant use signal using a redundant memory cell in place of a defective normal memory cell based on 2n (n is an integer of 2 or more) internal address signals Ai, Aib, Ai+1, Ai+1b for selecting an arbitrary one of a plurality of normal memory cells, and the information from a plurality of program circuits. The program circuits each comprise 2 redundant address program circuits RAP(i), RAP(i+1), and one redundant use program circuit RP. The redundant circuit comprises redundant address decoding circuits (100, 110) outputting a plurality of redundant address signals Rdi, Rdi+1. A redundant decoding circuit (120) outputs a redundant use signal R_E/D based on the redundant address signals Rdi, Rdi+1 and the information from the redundant use program circuit RP.
摘要翻译：基于2n（n为2以上的整数）的内部地址信号Ai，Aib，Ai + 1，Ai + 1b，使用冗余存储单元代替缺陷的正常存储单元输出冗余使用信号的冗余电路，用于选择多个正常存储单元中的任意一个，以及来自多个程序电路的信息。编程电路各自包括2个n-1个冗余地址编程电路RAP（i），RAP（i + 1）和一个冗余使用程序电路RP。冗余电路包括输出多个冗余地址信号Rdi，Rdi + 1的冗余地址解码电路（100,110）。冗余解码电路（120）基于冗余地址信号Rdi，Rdi + 1和来自冗余使用程序电路RP的信息输出冗余使用信号R_E / D。

4. 发明申请

WO1991014227A1 FIELD-PROGRAMMABLE REDUNDANCY APPARATUS FOR MEMORY ARRAYS 审中-公开
标题翻译：用于存储阵列的现场可编程冗余设备
公开(公告)号：WO1991014227A1
公开(公告)日：1991-09-19
申请号：PCT/US1991001289
申请日：1991-02-27
申请人： XICOR, INC.
发明人： XICOR, INC. , OWEN, William, H. , CAYWOOD, John , DRORI, Joseph , JAFFE, James , NOJIMA, Isao , SUNG, Jeffrey , WANG, Ping
IPC分类号： G06F11/20
CPC分类号： G11C29/789 , G11C29/835 , G11C29/838
摘要： A field-programmable redundancy apparatus (26, 87, 100) for integrated circuit semiconductor memory arrays (10) is disclosed. The present invention allows the user to replace a defective primary memory cell (36) with a redundant memory cell (86) while the integrated circuit memory array (10) is in the field. The user communicates with the redundancy apparatus (26, 87, 100) over the standard signal paths (12, 14, 16) with standard voltage levels of the integrated circuit semiconductor memory array (10). The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines (14, 16) of the memory array (10) to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus (26, 87, 100) provides information on the availability and functionality of the redundant memory cells (86) and allows the user to replace a defective primary memory cell (36) with a selected redundant memory cell (86). The present invention allows the user to perform in-field repairs of integrated circuit memory arrays, thus increasing the endurance and lifetime for these memory arrays.

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