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1. 发明申请

WO2008069383A1 METHOD AND APPARATUS FOR MODULO N CALCULATION 审中-公开
标题翻译：用于模数计算的方法和装置
公开(公告)号：WO2008069383A1
公开(公告)日：2008-06-12
申请号：PCT/KR2007/002971
申请日：2007-06-19
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE , CHO, Seong Chul , KIM, Hyung Jin , JO, Gweon Do , KIM, Jin Up , KIM, Dae Sik
发明人： CHO, Seong Chul , KIM, Hyung Jin , JO, Gweon Do , KIM, Jin Up , KIM, Dae Sik
IPC分类号： G06F7/57
CPC分类号： G06F7/72 , G06F7/727
摘要： A modulo N calculating method for an M1*M2-bit binary integer, wherein N, Ml and M2 are integers, includes the steps of dividing the M1*M2-bit binary integer into M1 bits and performing AND operation on each M1 bits and a specific binary integer; and changing a value of an output register depending on the AND operation result and storing the value thereto. A modulo N calculating apparatus includes an input unit for receiving an M1*M2-bit binary integer, wherein N, M1 and M2 are integers; and an AND operation unit for performing AND operation on the M1*M2-bit binary integer and a specific binary integer. Furthermore, when the M1 and the N may be 4 and 3, respectively, the specific binary value may be 1010 or 0101.
摘要翻译：对于M1×M2位二进制整数的模N计算方法，其中N，M1和M2是整数，包括以下步骤：将M1 * M2位二进制整数除以M1位，并对每个M1位和具体的二进制整数; 并根据AND运算结果改变输出寄存器的值并存储该值。模N计算装置包括用于接收M1 * M2位二进制整数的输入单元，其中N，M1和M2是整数; 以及AND运算单元，用于对M1 * M2位二进制整数和特定二进制整数进行AND运算。此外，当M1和N分别为4和3时，特定的二进制值可以是1010或0101。

2. 发明申请

WO2010048719A1 METHOD AND APPARATUS FOR MODULUS REDUCTION 审中-公开
标题翻译：用于模块减少的方法和装置
公开(公告)号：WO2010048719A1
公开(公告)日：2010-05-06
申请号：PCT/CA2009/001557
申请日：2009-10-30
申请人： CERTICOM CORP. , LAMBERT, Robert John
发明人： LAMBERT, Robert John
IPC分类号： G06F7/72 , G09C5/00 , H04L9/30
CPC分类号： H04L9/3066 , G06F7/72 , G06F7/727 , G06F7/728 , H04L9/3252 , H04L2209/043 , H04L2209/12
摘要： A modulo reduction is performed on a value α represented as an ordered sequence of computer readable words. The lowest order words are eliminated by substituting an equivalent value represented by higher order words for each of the lower order words. The lowest order words are eliminated until the sequence has a word length corresponding to the modulus. Carries and borrows resulting from the substitution are propagated from lower order words to higher order words. Further reduction is performed to maintain the word length of the sequence to that of the modulus. The further reduction may be determined by examination of a carryover bit or may be performed a predetermined number of times without examination.
摘要翻译：对表示为计算机可读字的有序序列的值a执行模减数。通过用较低阶单词表示的等价值代替每个低阶单词来消除最低阶单词。消除最低阶字，直到序列具有对应于模数的字长。由替代产生的携带和借款从低位词传播到高阶词。执行进一步的减少以将序列的字长保持为模数的字长。可以通过检查携带位来确定进一步的减少，或者可以在不进行检查的情况下执行预定次数。

3. 发明申请

WO2002088854A1 COMPUTATIONAL METHOD, SYSTEM, AND APPARATUS 审中-公开
标题翻译：计算方法，系统和装置
公开(公告)号：WO2002088854A1
公开(公告)日：2002-11-07
申请号：PCT/US2002/013513
申请日：2002-05-01
申请人： LAYER N NETWORKS, INC. , NORTH, Greg , HABAN, Scott , STEIN, Kyle
发明人： NORTH, Greg , HABAN, Scott , STEIN, Kyle
IPC分类号： G05B19/18
CPC分类号： G06F7/723 , B01L2300/049 , B01L2400/0633 , G01N2035/00247 , G01N2035/00574 , G06F7/72 , G06F7/727 , G06F7/728 , G11C7/1066
摘要： A method employed to improve the speed and efficiency of intense computational processing, wherein arguments are loaded into session memory and processed to provide an exponentiated resultant. The system includes a computing device and at least one computational apparatus (10), wherein the computing device is configured to use the computational apparatus to perform accelerated computations. The apparatus includes a chaining controller and a plurality of computational devices. A first chaining (20) subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.
摘要翻译：用于提高强烈计算处理的速度和效率的方法，其中参数被加载到会话存储器中并被处理以提供取幂的结果。该系统包括计算设备和至少一个计算设备（10），其中所述计算设备被配置为使用所述计算设备来执行加速计算。该装置包括链接控制器和多个计算装置。多个计算设备的第一链接（20）子集包括多个计算设备中的至少两个，并且链接控制器被配置为指示第一链接子集作为第一计算链进行操作。

4. 发明申请

WO99004531A1 METHOD AND APPARATUS FOR FAST ELLIPTICAL ENCRYPTION WITH DIRECT EMBEDDING 审中-公开
标题翻译：用于直接嵌入的快速ELLIPTICAL加密的方法和装置
公开(公告)号：WO99004531A1
公开(公告)日：1999-01-28
申请号：PCT/US1998/014892
申请日：1998-07-17
IPC分类号： G09C1/00 , G06F7/72 , H04L9/30 , H04L9/32
CPC分类号： G06F7/727 , G06F7/725 , H04L9/3066 , H04L9/3249
摘要： The present invention takes advantage of a quadratic-only ambiguity for x-coordinates in elliptic curve algebra as a means for encrypting plaintext directly onto elliptic curves. The encrypting of plaintext directly onto elliptic curves if refered to herein as "direct embedding". When performing direct embedding, actual plaintext is embedded as a "+" or "-" x-coordinate. The sender specifies using an extra bit whether + or - is used so that the receiver can decrypt appropriately. In operation their are two public initial x-coordinates such that two points P1 and P1 lie respectively on two curves E and E . A parcel of text xtext is selected that is no more than q bits in length. The curve (E or E ) that contains xtext is determined. A random number r is chosen and used to generate a coordinate x?q? using the public key of a receiving party. An elliptic add operation is used with the coordinate x?q? and the parcel of text to generate a message coordinate x?m?. A clue x?c? is generated using the random number and the point P from the appropriate curve E+/-. The sign that holds for xtext is determined and called g. The message coordinate m?m?, the clue x?c?, and the sign g are sent as a triple to the receiving party. The receiving party uses the clue x?c? and its private key to generate coordinate x?q?. Using the sign g and coordinate x?q?, the text can be recovered.
摘要翻译：本发明利用椭圆曲线代数中的x坐标的仅二次模糊度作为将明文直接加密到椭圆曲线上的手段。如果这里被称为“直接嵌入”，则将明文直接加密到椭圆曲线上。当执行直接嵌入时，实际明文被嵌入为“+”或“ - ”x坐标。发件人指定使用额外的位，无论是使用+还是 - ，以便接收方可以正确解密。在操作中，它们是两个公共初始x坐标，使得两个点P1 +和P1 < - >分别位于两条曲线E +和E - 上。选择一个不超过q位长度的文本xtext。确定包含xtext的曲线（E +或E - ）。随机数r被选择并用于生成坐标x？q？使用接收方的公钥。使用椭圆加法运算，坐标x？q？和文本的文本生成消息坐标x？m？。一个线索x？c？是使用随机数和来自适当曲线E +/-的点P生成的。确定xtext的符号，并称为g。消息坐标m？m？，线索x？c？和符号g作为三位元发送给接收方。接收方使用线索x？c？及其私钥生成坐标x？q？。使用符号g和坐标x？q？，可以恢复文本。

5. 发明申请

WO1993006672A1 METHOD AND APPARATUS FOR PUBLIC KEY EXCHANGE IN A CRYPTOGRAPHIC SYSTEM 审中-公开
标题翻译：公共关键交换系统中的方法与装置
公开(公告)号：WO1993006672A1
公开(公告)日：1993-04-01
申请号：PCT/US1992007864
申请日：1992-09-16
申请人： NEXT COMPUTER, INC.
发明人： NEXT COMPUTER, INC. , CRANDALL, Richard, E.
IPC分类号： H04L09/06
CPC分类号： H04L9/3066 , G06F7/725 , G06F7/727
摘要： The present invention is an elliptic curve cryptosystem (801, 802) that uses elliptic curves defined over finite fields, comprised of special classes of numbers. Special fast classes of numbers are used to optimize the modulo arithmetic required in the enciphering and deciphering process. The class of numbers used in the present invention is generally described by the form (901) 2q-C where C is an odd number and is relatively small, for example, no longer than the length of a computer word (16-32 bits). When a number is of this form (901), modulo arithmetic can be accomplished using shifts and adds only, eliminating the need for costly divisions. One subset of this fast class of numbers is known as 'Mersenne' primes, and are of the form 2q-1. Another class of numbers that can be used with the present invention are known as 'Fermat' numbers of the form 2q+1. The present invention provides a system (801, 802) whose level of security is tunable. q acts as an encryption bit depth parameter, such that larger values of q provide increased security. Inversion operations normally require an elliptic curve algebra can be avoided by selecting an inversionless parameterization of the elliptic curve (905). Fast Fourier transform for an FFT multiply mod operations optimized for efficient Mersenne arithmetic, allow the calculations of very large q to proceed more quickly than with other schemes.

6. 发明申请

WO2017201406A1 IMPLICIT RSA CERTIFICATES 审中-公开
标题翻译：隐含RSA证书
公开(公告)号：WO2017201406A1
公开(公告)日：2017-11-23
申请号：PCT/US2017/033541
申请日：2017-05-19
申请人： ARRIS ENTERPRISES LLC
发明人： MEDVINKSY, Alexander , SPRUNK, Eric J.
IPC分类号： H04L9/32
CPC分类号： H04L9/302 , G06F7/727 , H04L9/004 , H04L9/3249 , H04L9/3263
摘要： A secure digital communications method is provided in which a Certificate Authority generates an improved RSA key pair having a modulus, a public key exponent, a public key, and a private key. The public key exponent can contain descriptive attributes and a digital signature. The digital signature can be responsive to the descriptive attributes and the modulus. A secure session can be established between a first system and a second system, within a secure digital communication protocol. The second system can verify the digital signature to authenticate the public key.
摘要翻译：提供了一种安全的数字通信方法，其中证书机构生成具有模数，公钥指数，公钥和私钥的改进的RSA密钥对。公钥指数可以包含描述属性和数字签名。数字签名可以响应描述属性和模数。在安全数字通信协议内，可以在第一系统和第二系统之间建立安全会话。第二个系统可以验证数字签名来验证公钥。

7. 发明申请

WO2002089399A1 RING ARITHMETIC METHOD, SYSTEM, AND APPARATUS 审中-公开
标题翻译：环算术方法，系统和设备
公开(公告)号：WO2002089399A1
公开(公告)日：2002-11-07
申请号：PCT/US2002/013657
申请日：2002-05-01
申请人： LAYER N NETWORKS, INC. , MITCHELL, Oscar , DATTA, Rajat , STEIN, Kyle , BLAKLEY, George
发明人： MITCHELL, Oscar , DATTA, Rajat , STEIN, Kyle , BLAKLEY, George
IPC分类号： H04L9/28
CPC分类号： G06F7/72 , G01N2035/00247 , G01N2035/00574 , G06F7/723 , G06F7/727 , G06F7/728 , G06F13/1647 , G11C7/1066 , H04L9/302 , H04L47/125 , H04L63/0272 , H04L63/0428 , H04L63/166
摘要： A data encryption method performed with ring arithmetic operations using a residue number multiplication process wherein a first conversion to a first basis is done using a mixed radix system and a second conversion to a second basis is done using a mixed radix system. In some embodiments, a modulus C (96) is be chosen of the form 2 w - L, wherein C is a w-bit number and L is a low Hamming weight odd integer less than 2 (w-1)/2 . And in some of those embodiments, the residue mod C is calculated via several steps. P (98) is split into 2 w-bit words H 1 and L 1 (100). S 1 is calculated as equal to L 1 + (H 1 2 x1 ) + (H 1 2 x2 ) +...+ (H 1 2 xk ) + H 1 . S 1 is split into two w-bit words H 2 and L 2 . S 2 is computed as being equal to L 2 + (H 2 2 x1 ) + (H 2 2 x2 ) +...+ (H 2 2 xk ) + H 2 . S 3 is computed as being equal to S 2 + (2 x1 +...+ 2 xk + 1). And the residue is determined by comparing S 3 to 2 w . If S3 w , then the residue equals S 2 . If S 3 ≥ 2 w , then the residue equals S 3 - 2 w .
摘要翻译：利用残数乘法处理利用环算术运算执行的数据加密方法，其中使用混合基数系统完成到第一基础的第一转换，并且使用第二基础向第二基础转换到第二基础混合基数系统。在一些实施例中，模型C（96）被选择为形式2W-L，其中C是w位数并且L是小于2 （W-1）/ 2 。并且在这些实施例中的一些中，通过多个步骤来计算残余mod C. P（98）被分成2个w位字H 1和L 1（100）。 S 1被计算为等于L 1 +1（H 1×2×1）+（H×1） 1×2×2）+ ... +（H 1×2×K）+ H 1×2 。 S 1被分成两个w位字H 2和L 2。计算S 2 =等于L 2 +（H 2×2×1）+（H _{2×2×2）+ ... +（H 2×2×k）+ H 2× >。 S 3被计算为等于S 2 +（2·x 1 + ... + 2·xk·+ 1）。通过比较S 3到2 W来确定残余物。如果S3 < 2 w，那么残基等于S 2。如果S 3≥2W，那么残基等于S 3 -2 W 。}

8. 发明申请

WO2002088969A1 CONTROLLER ARCHITECTURE AND STRATEGY FOR SMALL DISCONTIGUOUS ACCESSES TO HIGH-DENSITY MEMORY DEVICES 审中-公开
标题翻译：小型不连续访问高密度存储设备的控制器架构和策略
公开(公告)号：WO2002088969A1
公开(公告)日：2002-11-07
申请号：PCT/US2002/013512
申请日：2002-05-01
申请人： LAYER N NETWORKS, INC. , ZSOHAR, Leslie
发明人： ZSOHAR, Leslie
IPC分类号： G06F13/00
CPC分类号： G06F13/1647 , G01N2035/00247 , G01N2035/00574 , G06F7/72 , G06F7/723 , G06F7/727 , G06F7/728 , G11C7/1066 , H04L47/125 , H04L63/0272 , H04L63/0428 , H04L63/166
摘要： A memory architecture design (20) providing low latency read or write access especially for small blocks stored as discontiguous data in high-density storage memory devices (22), such as bank switched DDR-SDRAM (26), by buffering and prioritizing memory requests according to their timing cycles (190, 290, 490).
摘要翻译：一种存储架构设计（20），通过缓冲和优先化存储器请求，提供低等待时间的读或写访问，特别是对于存储为诸如存储体交换DDR-SDRAM（26）的高密度存储存储器件（22）中的不连续数据的小块，根据它们的时序周期（190,290,490）。

9. 发明申请

WO02008885A1 HIGH-SPEED PARALLEL-PREFIX MODULO 2-1 ADDERS 审中-公开
标题翻译：高速并行前缀模块2 -1 ADDERS
公开(公告)号：WO02008885A1
公开(公告)日：2002-01-31
申请号：PCT/US2001/022247
申请日：2001-07-16
IPC分类号： G06F7/50 , G06F7/508 , G06F7/72 , G06F7/38
CPC分类号： G06F7/727 , G06F7/508 , G06F2207/5063
摘要： A parallel-prefix modulo 2 -1 adder (201) that is as fast as the fastest parallel prefix 2 integer adders, does not require an extra level of logic to generate the carry values, and has a very regular structure to which pipeline registers can easily be added. All nodes of the adder have a fanout n stages in the prefix structure. Each stage has n logical operators, and all of the logical operators in the prefix structure are of the same kind. Pipeline registers may be inserted before and/or after a stage in the prefix structure.
摘要翻译：与最快的并行前缀2 整数加法器一样快的并行前缀模2 n -1加法器（201）不需要额外级别的逻辑来生成进位值，并且具有非常规则可以轻松添加流水线寄存器的结构。在加法器的前缀结构（203）中，由并行前缀结构输出的每个进位值项由输入到加法器的操作数中的所有比特来确定。在一个实施例中，在前缀结构中存在log2n阶段。每个阶段都有n个逻辑运算符，前缀结构中的所有逻辑运算符都是相同的。可以在前缀结构中的阶段之前和/或之后插入管道寄存器。

10. 发明申请

WO2008005592A1 COMPUTATION OF A MOD (2 N - 1) 审中-公开
标题翻译： MOD（2 N - 1）的计算
公开(公告)号：WO2008005592A1
公开(公告)日：2008-01-10
申请号：PCT/US2007/064370
申请日：2007-03-20
申请人： VIA TELECOM CO., LTD. , SHEN, Qiang
发明人： SHEN, Qiang
IPC分类号： G06F7/72
CPC分类号： G06F7/727
摘要： A system and method for computing A mod (2 n -1), where A is an m bit quantity, where n is a positive integer, where m is greater than or equal to n. The quantity A may be partitioned into a plurality of sections, each being at most n bits long. The value A mod (2 n -1) may be computed by adding the sections in mod(2 n -1) fashion. This addition of the sections of A may be performed in a single clock cycle using an adder tree, or, sequentially in multiple clock cycles using a two-input adder circuit provided the output of the adder circuit is coupled to one of the two inputs. The computation A mod (2 n -1) may be performed as a part of an interleaving/deinterleaving operation, or, as part of an encryption/decryption operation.
摘要翻译：一种用于计算A mod（2-n-1）的系统和方法，其中A是m比特量，其中n是正整数，其中m大于或等于n。数量A可以被划分成多个部分，每个部分最多n位长。可以通过以mod（2-n -I-1）方式加上这些部分来计算值A mod（2≤n≤-1）。可以使用加法器树在单个时钟周期中执行A的这些部分的添加，或者使用双输入加法器电路在多个时钟周期中顺序地执行，只要加法器电路的输出耦合到两个输入中的一个。作为交织/解交织操作的一部分，或作为加密/解密操作的一部分，可以执行计算A mod（2-n-1）。

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