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1. 发明申请

WO2018034769A1 VOTING CIRCUIT AND SELF-CORRECTING LATCHES 审中-公开
标题翻译：表决电路和自我修正的锁存器
公开(公告)号：WO2018034769A1
公开(公告)日：2018-02-22
申请号：PCT/US2017/042549
申请日：2017-07-18
申请人： XILINX, INC.
发明人： NGUYEN, Chi, M. , FU, Robert, I.
IPC分类号： H03K19/003 , H03K19/23
摘要： The disclosed voting circuit includes a pull-up circuit (110) connected to an output node (126) and to a positive supply voltage (122). A pull-down circuit (112) is connected to the output node (126) and to ground (124), and the output node (126) is coupled to receive true output of a first bi-stable circuit (104). The pull-up circuit (1 10) pulls the output node (126) to the positive supply voltage in response to complementary output signals from second (106) and third (108) bistable circuits being in a first state, and the pull-down circuit (1 12) pulls the output node (126) to ground (124) in response to complementary output signals from second (106) and third (108) bi-stable circuits being in a second state that is opposite the first state.
摘要翻译：所公开的投票电路包括连接到输出节点（126）和正电源电压（122）的上拉电路（110）。下拉电路（112）连接到输出节点（126）和接地（124），并且输出节点（126）被耦合以接收第一双稳态电路（104）的真实输出。响应于来自第二（106）和第三（108）双稳电路的互补输出信号处于第一状态，上拉电路（110）将输出节点（126）拉至正电源电压，并且下拉响应于来自第二（106）和第三（108）双稳电路的互补输出信号处于与第一状态相反的第二状态，电路（112）将输出节点（126）拉到地（124） / p>

2. 发明申请

WO2019125781A1 SELECTIVELY PROVIDING CLOCK SIGNALS USING A PROGRAMMABLE CONTROL CIRCUIT 审中-公开
公开(公告)号：WO2019125781A1
公开(公告)日：2019-06-27
申请号：PCT/US2018/064315
申请日：2018-12-06
申请人： XILINX, INC.
发明人： GAIDE, Brian, C. , GANUSOV, Ilya, K. , NGUYEN, Chi, M. , FU, Robert, I.
IPC分类号： H03K5/15 , H03K19/177
摘要： The disclosed circuit arrangements include a logic circuit (105), input register logic (104) coupled to the logic circuit and including a first plurality of bistable circuits (202) and a control circuit (102) coupled to the input register logic. The control circuit is configured to generate a plurality of delayed clock signals (142, 148, 306, 308, 320, 326, 414, 416) from an input clock signal (150). The plurality of delayed clock signals include a first delayed clock signal (142, 148, 306, 308, 320, 326, 414, 416) and a second delayed clock signal (142, 148, 306, 308, 320, 326, 414, 416). The control circuit selectively provides one or more of the delayed clock signals or the input clock signal to clock inputs of the first plurality of bi-stable circuits and selectively provides one or more of the delayed clock signals or the input clock signal to the logic circuit. The control circuit includes a variable clock delay logic (302) circuit configured to equalize a clock delay to the input register logic with a clock delay to the logic circuit.

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