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2. 发明申请

WO0237686A3 METHOD AND APPARATUS FOR CONTROLLING STAGES OF A MULTI-STAGE CIRCUIT 审中-公开
标题翻译：用于控制多级电路阶段的方法和装置
公开(公告)号：WO0237686A3
公开(公告)日：2004-02-19
申请号：PCT/US0146188
申请日：2001-10-31
申请人： QUALCOMM INC
发明人： BAZARJANI SEYFOLLAH , WANG SEAN , PELUSO VINCENZO
IPC分类号： H03M3/02
CPC分类号： H03M3/32 , H03M3/394 , H03M3/406 , H03M3/418 , H03M3/47
摘要： A control mechanism that can be used to control a SIGMA DELTA to provide the required level of performance while reducing power consumption. The SIGMA DELTA ADC is designe dwith multiple stage (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMA DELTA ADC that is similar to the SIGMA DELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditined samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMA DELTA stages in the SIGMA DELTA ADC.
摘要翻译：一种可用于控制SIGMA DELTA以提供所需性能水平同时降低功耗的控制机制。 SIGMA DELTA ADC设计为多级（即，环路或部分），并且随着更多级的启用，提供改进的性能（例如，更高的动态范围）。控制机构选择性地实现足够数量的级以提供所需性能并且禁用剩余级以节省功率。控制机制通过测量信号路径上类似于SIGMA DELTA ADC的SIGMA DELTA ADC的ADC输入信号的一个或多个特性（例如，信号电平）来实现这一点，将测量特性与特定阈值进行比较级别，并控制阶段以达到所需目标。在一个实现中，控制电路包括一个或多个检测器级，调理电路和信号处理器。检测器级接收输入信号并提供检测信号。调理电路接收检测到的信号并提供条件样本。信号处理器接收经调节的样本并提供选择性地禁用SIGMA DELTA ADC中的零个或更多个SIGMA DELTA级的控制信号。

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