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1. 发明申请

WO2009050673A1 MAGNETIC FIELD SENSOR 审中-公开
标题翻译：磁场传感器
公开(公告)号：WO2009050673A1
公开(公告)日：2009-04-23
申请号：PCT/IB2008/054261
申请日：2008-10-16
申请人： NXP B.V. , ZIEREN, Victor , WOLTERS, Robertus, A., M.
发明人： ZIEREN, Victor , WOLTERS, Robertus, A., M.
IPC分类号： G01R33/06 , H01L43/06
CPC分类号： G01R33/06 , G01R33/0088 , G01R33/066
摘要： The invention relates to a magnetic field sensor comprising a substrate having a first side (S1). The substrate comprises at the first side (S1) a silicon comprising semiconductor layer (P-SUB) which comprises a buried N-well (DNW). A bipolar transistor having an emitter region (PE+, NE+), a base region (PB+, NB+), and a first collector region (CLR1) and a second collector region, is provided in the silicon comprising semiconductor layer (P-SUB). The emitter region (PE+, NE+) is located at the first side (S1) above the buried N-well (DNW). According to the invention the bipolar transistor is arranged such that, in operation, a part of an emitter current (IEM) that traverses the base region (PB+, NB+) is distributed over the first and second collector regions (CLR1, CLR2) obtaining a first and a second collector current (ICL1, ICL2), wherein a difference between the first and second collector currents (ICL1, ICL2) is determined by a magnetic field component (B x, B z ) perpendicular to a current plane. A bipolar magneto-transistor structure is obtained which is compatible with triple-well technology and that is sensitive to magnetic fields in a direction perpendicular to the current plane. The magnetic field sensor is compatible with triple-well technology and has a high linearity and a high sensitivity. The invention further relates to an integrated circuit comprising such magnetic field sensor (Snsr) and a card provided with such integrated circuit.
摘要翻译：本发明涉及一种包括具有第一侧（S1）的衬底的磁场传感器。衬底在第一侧（S1）包括包含半导体层（P-SUB）的硅，其包括掩埋的N阱（DNW）。在包含硅的半导体层（P-SUB）中设置具有发射极区域（PE +，NE +），基极区域（PB +，NB +）和第一集电极区域（CLR1）和第二集电极区域的双极晶体管。发射极区域（PE +，NE +）位于掩埋N阱（DNW）上方的第一侧（S1）。根据本发明，双极晶体管被布置成使得在工作中，遍及基极区域（PB +，NB +）的一部分发射极电流（IEM）分布在第一和第二集电极区域（CLR1，CLR2）上，从而获得第一和第二集电极电流（ICL1，ICL2），其中第一和第二集电极电流（ICL1，ICL2）之间的差由垂直于当前平面的磁场分量（B x，B z）确定。获得了与三阱技术兼容并且在垂直于当前平面的方向上对磁场敏感的双极磁 - 晶体管结构。磁场传感器与三井技术兼容，具有高线性度和高灵敏度。本发明还涉及包括这种磁场传感器（Snsr）的集成电路和设置有该集成电路的卡。

2. 发明申请

WO2009050672A2 MAGNETIC DETECTION OF BACK-SIDE LAYER 审中-公开
标题翻译：背面层的磁性检测
公开(公告)号：WO2009050672A2
公开(公告)日：2009-04-23
申请号：PCT/IB2008/054260
申请日：2008-10-16
申请人： NXP B.V. , ZIEREN, Victor , WOLTERS, Robertus, A., M.
发明人： ZIEREN, Victor , WOLTERS, Robertus, A., M.
CPC分类号： H01L23/57 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/12032 , H01L2924/1305 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to an integrated circuit comprising a substrate having a first side and a second opposing side. An electronic circuit (EC) is provided at the first side (S1) of the substrate, wherein the electronic circuit (EC) comprises at least one magnetic field sensor (Snsr, Snsr1, Snsr2, Snsr3, Snsr4). The integrated circuit further comprises a magnetizable region (MR) provided on the second side (S1) of the substrate (SUB) by using a wafer-level type deposition processing step. The magnetic moment of the magnetizable region (MR) is configurable for generating a magnetic field (H1, H2) detectable at the location of the at least one magnetic field sensor (Snsr, Snsr1, Snsr2, Snsr3, Snsr4). The integrated circuit constitutes a very simple construction and enables a strongly miniaturized solution which is, because of its reduced dimensions well suitable for being used in bank cards. An attempt to remove the integrated circuit according to the invention from its environment (e.g. a bank card) may result in the magnetizable region (MR) getting damaged (partially removed) or even completely removed. The invention provides a first level of security against external attack. Embodiments of the invention provide higher security levels. Various magnetic field sensors are illustrated which may be advantageously integrated in the integrated circuit. The invention also relates to a card provided with such integrated circuit. The card in accordance with the invention is more secure. The invention further relates to a method of initializing such integrated circuit and a method of checking the authenticity of such integrated circuit.
摘要翻译：本发明涉及一种集成电路，其包括具有第一侧和第二相对侧的衬底。电子电路（EC）设置在基板的第一侧（S1），其中电子电路（EC）包括至少一个磁场传感器（Snsr，Snsr1，Snsr2，Snsr3，Snsr4）。集成电路还包括通过使用晶片级型沉积处理步骤在衬底（SUB）的第二侧（S1）上设置的可磁化区域（MR）。可磁化区域（MR）的磁矩可配置为产生在至少一个磁场传感器（Snsr，Snsr1，Snsr2，Snsr3，Snsr4）的位置处可检测的磁场（H1，H2）。集成电路构成了非常简单的结构，并且能够实现强大的小型化解决方案，因为其尺寸很小，非常适合用于银行卡。根据本发明从其环境（例如银行卡）去除集成电路的尝试可能导致可磁化区域（MR）被损坏（部分移除）或甚至完全去除。本发明提供了抵御外部攻击的第一级安全性。本发明的实施例提供更高的安全级别。示出了可以有益地集成在集成电路中的各种磁场传感器。本发明还涉及一种具有该集成电路的卡。根据本发明的卡更安全。本发明还涉及一种初始化这种集成电路的方法和一种检查这种集成电路的真实性的方法。

3. 发明申请

WO2008099348A3 SEMICONDUCTOR DEVICE IDENTIFIER GENERATION 审中-公开
公开(公告)号：WO2008099348A3
公开(公告)日：2008-08-21
申请号：PCT/IB2008/050515
申请日：2008-02-13
申请人： NXP B.V. , ZIEREN, Victor , VAN GELOVEN, Johannes, A., J. , WOLTERS, Robertus, A., M.
发明人： ZIEREN, Victor , VAN GELOVEN, Johannes, A., J. , WOLTERS, Robertus, A., M.
IPC分类号： G11C7/20 , G11C11/4072 , G11C7/10 , H01L23/58 , G11C7/24 , G11C7/04
摘要： The present invention relates to a semiconductor device (11) for generating an identifier comprising a volatile memory (13) having a plurality of memory cells (21), to a method of generating an identifier using such a semiconductor device (11) and to a method of detecting a tampering on said semiconductor device (11). Providing a layer (27) comprising conductive and non conductive materials (28, 29) with said semiconductor device allows for a cooperation between elements or properties of a memory cell (21) which are responsible for the assuming of a random state by the memory cell (21) during initialization and the layer (27) acting as stray capacitances (26, 26 ). From the random states of the memory cells (21) a key or identifier can be generated. Due to said cooperation, i.e. the influence of the stray capacitances (26, 26 ) formed by the layer, the key or identifier can be generated more reliably over a wider range of operation parameters. Further, a tampering on said layer (27) leads to a change to the stray capacitances (26, 26 ) and thus changes the identifier or key.

4. 发明申请

WO2009144608A1 DETECTION CIRCUITRY FOR DETECTING BONDING CONDITIONS ON BOND PADS 审中-公开
标题翻译：用于检测粘合剂粘合条件的检测电路
公开(公告)号：WO2009144608A1
公开(公告)日：2009-12-03
申请号：PCT/IB2009/051991
申请日：2009-05-14
申请人： NXP B.V. , ZIEREN, Victor , BENTEN, Harold Geradus Pieter Hendrikus , BARGAGLI-STOFFI, Agnese Antonietta Maria , PELGROM, Marcel , VEENDRICK, Hendricus Joseph Maria
发明人： ZIEREN, Victor , BENTEN, Harold Geradus Pieter Hendrikus , BARGAGLI-STOFFI, Agnese Antonietta Maria , PELGROM, Marcel , VEENDRICK, Hendricus Joseph Maria
IPC分类号： G01R31/04 , H01L23/485
CPC分类号： G01R31/2884 , G01R31/048 , H01L22/34 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05551 , H01L2224/05554 , H01L2224/05578 , H01L2224/05599 , H01L2224/13 , H01L2224/13028 , H01L2224/13099 , H01L2224/1613 , H01L2224/859 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01051 , H01L2924/01057 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/00
摘要： The present invention relates to a detection circuitry for detecting bonding conditions on segmented bond pads of a semiconductor device, the bonding conditions representing good or bad contacts on the bond pads. The detection circuitry comprises a segmented bond pad (1, 11) having at least two parts (2, 3, 12, 13) being electrically separated from each other, and a supplying unit (S1, S2, R1, R2) being adapted for supplying predetermined signals to at least one of the at least two parts of the segmented bond pad. Furthermore, a detector (4, 14) is provided for receiving from at least one of the at least two parts of the segmented bond pad sensing signals derived from said predetermined signals, and for determining the bonding conditions based on said received sensing signals indicative of a good or bad bonding contact on the segmented bond pad.
摘要翻译：本发明涉及一种用于检测半导体器件的分段接合焊盘上的接合条件的检测电路，所述接合条件表示接合焊盘上的良好或不良接触。所述检测电路包括具有彼此电分离的至少两个部分（2,3,13,13）的分段接合焊盘（1,11），以及供应单元（S1，S2，R1，R2），适于向分段接合焊盘的至少两个部分中的至少一个提供预定信号。此外，提供检测器（4,14），用于从分段焊接感测信号的至少两个部分中的至少一个接收从所述预定信号导出的感测信号，并且用于基于所述接收的感测信号来确定指示在分段接合垫上的良好或不良的接合接触。

5. 发明申请

WO2010041221A1 CURRENT SENSOR AND CURRENT SENSING METHOD 审中-公开
标题翻译：电流传感器和电流传感方法
公开(公告)号：WO2010041221A1
公开(公告)日：2010-04-15
申请号：PCT/IB2009/054436
申请日：2009-10-09
申请人： NXP B.V. , ZIEREN, Victor
发明人： ZIEREN, Victor
IPC分类号： G01R15/20
CPC分类号： G01R15/20
摘要： A current sensor, comprises an input conductor (IN) which is supplied with the current to be sensed and an output conductor (OUT) from which the current to be sensed is output. A conductor path is provided between the input conductor and the output conductor, wherein the path is provided on a first, movable element (1 ) and a second, fixed element (2). The path defines a pair of adjacent path portions (3,5; 3;4), one of the path portions (4;5) on the fixed element and the other (3) on one side of the movable element. An arrangement detects movement of the movable element to determine the current flowing. This arrangement uses a conductor path which can be part of the circuit being tested, and thereby does not require any additional components, other than the movement detector.
摘要翻译：电流传感器包括输入导体（IN），输入导体（IN）被提供有待检测的电流和输出导体（OUT），输出电流被输出。导体路径设置在输入导体和输出导体之间，其中路径设置在第一可移动元件（1）和第二固定元件（2）上。该路径限定一对相邻的路径部分（3,5; 3; 4），固定元件上的路径部分（4; 5）中的一个和可移动元件的一侧上的另一个（3）。一种装置检测可移动元件的运动以确定电流流动。这种布置使用可以作为被测电路的一部分的导体路径，从而不需要除运动检测器之外的任何附加部件。

6. 发明申请

WO2009144669A1 DLL FOR PERIOD JITTER MEASUREMENT 审中-公开
标题翻译： DLL用于定期测试
公开(公告)号：WO2009144669A1
公开(公告)日：2009-12-03
申请号：PCT/IB2009/052214
申请日：2009-05-27
申请人： NXP B.V. , PELGROM, Marcel J., M. , VEENDRICK, Hendricus, Joseph, Maria , ZIEREN, Victor
发明人： PELGROM, Marcel J., M. , VEENDRICK, Hendricus, Joseph, Maria , ZIEREN, Victor
IPC分类号： G01R31/317
CPC分类号： G01R31/31709
摘要： A sensor (400) for sensing jitter in a clock signal has a DLL (402, 310, 312) for locking a clock signal and a delayed version of the clock signal. The sensor comprises a delay line (402) having a first number of cascaded controllable delay segments. The DLL uses a second number of the cascaded delay segments for generating a delay of an average clock period of the clock signal. The second number is smaller than the first number. The sensor also has a comparator (408) for supplying a sensor output signal representative ofa comparison of the clock signal and a further delayed version of the clock signal. The further delayed version of the clock signal is obtained from an output of a specific one of the delay segments located in the delay line after the second number of cascaded delay segments.
摘要翻译：用于感测时钟信号中的抖动的传感器（400）具有用于锁定时钟信号和时钟信号的延迟版本的DLL（402,310,312）。传感器包括具有第一数量级联的可控延迟段的延迟线（402）。 DLL使用第二数量的级联延迟段来产生时钟信号的平均时钟周期的延迟。第二个数字小于第一个数字。传感器还具有比较器（408），用于提供表示时钟信号和时钟信号的进一步延迟版本的比较的传感器输出信号。时钟信号的进一步延迟版本是从第二级联延迟段之后的位于延迟线中的特定延迟段的输出获得的。

7. 发明申请

WO2010064161A1 A SIMPLE AND STABLE REFERENCE FOR IR-DROP AND SUPPLY NOISE MEASUREMENTS 审中-公开
标题翻译：用于IR-DROP和供应噪声测量的简单和稳定的参考
公开(公告)号：WO2010064161A1
公开(公告)日：2010-06-10
申请号：PCT/IB2009/055139
申请日：2009-11-18
申请人： NXP B.V. , VEENDRICK, Hendricus Joseph Maria , PELGROM, Marcel , ZIEREN, Victor
发明人： VEENDRICK, Hendricus Joseph Maria , PELGROM, Marcel , ZIEREN, Victor
IPC分类号： G01R31/30 , G01R19/165
CPC分类号： G01R31/3004 , G01R19/16552 , G01R19/16571
摘要： Apparatus and method for IR-drop and supply noise measurements in electronic circuits. A first voltage at a point of interest in the circuit is sampled and stored during a quiescent mode of the circuit the voltage is to be measured in. Subsequently, the circuit is brought in an operating mode and a second voltage is sampled and held at the same point of interest. The first and the second voltage are compared and a corresponding voltage signal is passed to a system output.
摘要翻译：电子电路中红外降噪和噪声测量的装置和方法。电路中的感兴趣点处的第一电压被采样并在电路的静态模式下被存储。随后，电路进入操作模式，并且将第二电压采样并保持在同样的兴趣点。比较第一和第二电压，并将相应的电压信号传递到系统输出。

8. 发明申请

WO2009104130A2 POWER SUPPLY SWITCHING FOR REDUCING POWER CONSUMPTION OF INTEGRATED CIRCUITS 审中-公开
标题翻译：用于降低集成电路功耗的电源开关
公开(公告)号：WO2009104130A2
公开(公告)日：2009-08-27
申请号：PCT/IB2009/050638
申请日：2009-02-17
申请人： NXP B.V. , VEENDRICK, Hendricus, J., M. , PELGROM, Marcel , ZIEREN, Victor
发明人： VEENDRICK, Hendricus, J., M. , PELGROM, Marcel , ZIEREN, Victor
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： Reduction of power consumption of integrated circuits due to reduced leakage is provided by driving an integrated circuit with a first drive potential (Vdd) and a second drive potential (Vsscore), switching the second drive potential to a ground potential in active mode using a power switch (30), and connecting a substrate potential of the integrated circuit to the ground potential.
摘要翻译：通过驱动具有第一驱动电位（Vdd）和第二驱动电位（Vsscore）的集成电路来提供由于减少泄漏而降低集成电路的功耗，使用功率将第二驱动电位切换到处于主动模式的接地电位开关（30），并将集成电路的衬底电位连接到地电位。

9. 发明申请

WO2012119900A1 MAGNETIC SENSORS 审中-公开
标题翻译：磁传感器
公开(公告)号：WO2012119900A1
公开(公告)日：2012-09-13
申请号：PCT/EP2012/053419
申请日：2012-02-29
申请人： NXP B.V. , ZIEREN, Victor , VAN VELDHOVEN, Robert , WUNNICKE, Olaf , TUINHOUT, Hans
发明人： ZIEREN, Victor , VAN VELDHOVEN, Robert , WUNNICKE, Olaf , TUINHOUT, Hans
IPC分类号： G01R33/06 , H01L29/82 , G01R33/00
CPC分类号： G01R35/005 , G01R33/0035 , G01R33/06 , G01R33/066 , H01L29/82
摘要： The disclosure relates to the field of magnetic sensors, sensor governing circuits and associated methods. Certain disclosed embodiments relate to semiconductor (e.g. silicon-based) magnetic sensors, including a magnetic sensor assembly comprising a semiconductor layer (17), the semiconductor layer comprising a first collector (113) and a second collector (114), a first emitter (111) and a second emitter (112); and a governing circuit (120) configured to control and measure current flow independently between the first collector and first emitter in a first direction, and between the second collector and second emitter in a second opposing direction.
摘要翻译：本公开涉及磁传感器，传感器控制电路和相关方法领域。某些公开的实施例涉及半导体（例如基于硅的）磁传感器，包括包括半导体层（17）的磁传感器组件，该半导体层包括第一集电极（113）和第二集电极（114），第一发射极 111）和第二发射器（112）; 以及配置成在第一方向上在第一集电器和第一发射极之间以及在第二相对方向上在第二集电极和第二发射极之间独立地控制和测量电流的控制电路（120）。

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