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1. 发明申请

WO2009034543A1 A SIGNAL SAMPLING CIRCUIT 审中-公开
标题翻译：信号采样电路
公开(公告)号：WO2009034543A1
公开(公告)日：2009-03-19
申请号：PCT/IB2008/053682
申请日：2008-09-12
申请人： NXP B.V. , LOUWSMA, Simon, Minze , VERTREGT, Maarten
发明人： LOUWSMA, Simon, Minze , VERTREGT, Maarten
IPC分类号： G11C27/02
CPC分类号： G11C27/02 , G11C27/024
摘要： A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital converter via a respective output switch. The output switch of each channel opens for a tracking time period when the track-and-hold circuit is in a tracking mode for sampling the signal, and closes for a holding time period when the track-and- hold circuit is in a holding mode for outputting the sampled signal. The holding time period comprises a settling time period that is at least as long as the tracking time period. The settling time period is used by the track-and-hold circuit to charge an input capacitance of the analogue to digital converter to a voltage according to the sampled signal.
摘要翻译：公开了一种用于采样信号的采样电路。采样电路包括适合以时分复用方式对信号进行采样的多个采样通道，每个采样通道包括通过相应的输出开关连接到相应的模数转换器的相应的跟踪和保持电路。当跟踪和保持电路处于用于对信号进行采样的跟踪模式时，每个通道的输出开关打开跟踪时间段，并且当跟踪保持电路处于保持模式时关闭保持时间段用于输出采样信号。保持时间段包括至少与跟踪时间段一样长的建立时间段。跟踪和保持电路使用建立时间段，以将模数转换器的输入电容根据采样信号充电至电压。

2. 发明申请

WO2009034518A2 TIME-INTERLEAVED TRACK AND HOLD 审中-公开
标题翻译：时间交错跟踪和保持
公开(公告)号：WO2009034518A2
公开(公告)日：2009-03-19
申请号：PCT/IB2008/053628
申请日：2008-09-09
申请人： NXP B.V. , LOUWSMA, Simon Minze , VERTREGT, Maarten
发明人： LOUWSMA, Simon Minze , VERTREGT, Maarten
IPC分类号： G11C27/02
CPC分类号： H03K19/018528 , G11C27/026
摘要： The present application relates to an apparatus comprising a first transistor element, with at least three terminals, and at least one switching unit. The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus. The apparatus comprises a first transistor element with at least three terminals, wherein a first terminal is supplied with a first voltage, and wherein a second terminal is supplied with a second voltage. The apparatus comprises a first switching unit, wherein a third terminal is connected to ground potential via the first switching unit. The transistor element comprises a predefined threshold voltage. The first voltage and the second voltage are predefined alternating voltages. The transistor element is configured such that in case a differential voltage between the first predefined alternating voltage and the second predefined alternating voltage is higher than the predefined threshold voltage and the first switching unit is not conductive the third terminal is charged with the first predefined alternating voltage.
摘要翻译：本申请涉及一种装置，该装置包括具有至少三个端子的第一晶体管元件和至少一个开关单元。本申请还涉及一种方法，其上存储有计算机程序的计算机可读介质以及包括该设备的跟踪和保持电路。该装置包括具有至少三个端子的第一晶体管元件，其中第一端子被提供有第一电压，并且其中第二端子被提供有第二电压。该装置包括第一开关单元，其中第三端子经由第一开关单元连接到地电位。晶体管元件包括预定义的阈值电压。第一电压和第二电压是预定义的交流电压。晶体管元件被配置为使得在第一预定义交流电压和第二预定义交流电压之间的差分电压高于预定义阈值电压并且第一开关单元不导通的情况下，第三端子以第一预定义交流电压

3. 发明申请

WO2007116325A3 SECURITY STORAGE OF ELECTRONIC KEYS WITHIN VOLATILE MEMORIES 审中-公开
公开(公告)号：WO2007116325A3
公开(公告)日：2007-10-18
申请号：PCT/IB2007/050495
申请日：2007-02-15
申请人： NXP B.V. , TUYLS, Pim , VERTREGT, Maarten , DE JONG, Hans , LIST, Frans , WAGNER, Mathias , ZACHARIASSE, Frank , MELS, Arjan
发明人： TUYLS, Pim , VERTREGT, Maarten , DE JONG, Hans , LIST, Frans , WAGNER, Mathias , ZACHARIASSE, Frank , MELS, Arjan
IPC分类号： G06F21/00
摘要： It is described a method for providing an electronic key within an integrated circuit (100) including both a volatile memory (102) and a non-volatile memory (104). The described comprises starting up the integrated circuit (100), reading the logical state of predetermined data storage cells (102a) assigned to the volatile memory (102), which data storage cells (102a) are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (102a). Preferably, the predetermined data storage cells (102a) are randomly distributed within the volatile memory (102). It is further described an integrated circuit (100) for providing an electronic key. The integrated circuit (100) comprises a volatile memory (102) comprising predetermined data storage cells (102a), which are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and a non-volatile memory (104) having information stored upon regarding the predetermined data storage cells (102a). Thereby, the electronic key is defined by the corresponding logical states of the predetermined data storage cells (102a).

4. 发明申请

WO2007069160A1 FLASH ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：闪光模拟数字转换器
公开(公告)号：WO2007069160A1
公开(公告)日：2007-06-21
申请号：PCT/IB2006/054704
申请日：2006-12-08
申请人： NXP B.V. , PELGROM, Marcel , KATOCH, Atul , VERTREGT, Maarten
发明人： PELGROM, Marcel , KATOCH, Atul , VERTREGT, Maarten
IPC分类号： H03M1/06
CPC分类号： H03M1/0673 , H03M1/365
摘要： A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.
摘要翻译：闪存模数转换器包括由参考电压源供电的电阻串，用于提供一组等距参考电压，以及一组用于将模拟输入信号与参考电压进行比较的比较器。一组开关被布置和控制以执行用于减轻组件之间的错配的影响的算法。开关布置在参考电压源和电阻串之间，从而避免了比较器的参考输入中的开关。电阻串优选为圆形。转换器可以处理差分信号。

5. 发明申请

WO2009022304A2 SECURE STORAGE OF A CODEWORD WITHIN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：安全存储一个集成电路内的代码
公开(公告)号：WO2009022304A2
公开(公告)日：2009-02-19
申请号：PCT/IB2008/053253
申请日：2008-08-13
申请人： NXP B.V. , PELGROM, Marcel , VERTREGT, Maarten , TUINHOUT, Hans, Paul
发明人： PELGROM, Marcel , VERTREGT, Maarten , TUINHOUT, Hans, Paul
IPC分类号： G11C17/12
CPC分类号： G11C7/24 , G11C11/41
摘要： The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (μA, μB, μC) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.
摘要翻译：本发明公开了一种用于安全地存储码字的集成电路（10）。码字的值取决于集成电路的至少一个晶体管（TRA，TRB，TRC）的迁移率（μA，μB，μC）。本发明还公开了一种读取器装置（15），一种用于确定来自集成电路（10）的码字的值的方法，以及一种用于改变码字的值的方法。

6. 发明申请

WO2008149259A3 CIRCUIT WITH A SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER 审中-公开
公开(公告)号：WO2008149259A3
公开(公告)日：2008-12-11
申请号：PCT/IB2008/052080
申请日：2008-05-27
申请人： NXP B.V. , LOUWSMA, Simon, M. , VERTREGT, Maarten
发明人： LOUWSMA, Simon, M. , VERTREGT, Maarten
IPC分类号： H03M1/46
摘要： During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and compared to the analog input signal. The digital reference values are selected dependent on comparison results. In the selection of the digital reference values successive steps between digital reference values are each selected dependent on values of the comparator result from a plurality of preceding recursion cycles. The comparison results define a series of successively narrower ranges of digital values that contain a digital representation of the analog input signal. Use of a plurality of comparator results for selecting the steps in the digital reference values makes it possible to reduce uncertainty about whether the comparison result has settled. This in turn makes it possible to reduce the sizes of the successive ranges, which speeds up convergence.

7. 发明申请

WO2010010518A1 CIRCUIT COMPRISING A VARACTOR DEVICE 审中-公开
标题翻译：包含变压器装置的电路
公开(公告)号：WO2010010518A1
公开(公告)日：2010-01-28
申请号：PCT/IB2009/053172
申请日：2009-07-22
申请人： NXP B.V. , VAN DER WEL, Arnoud , VERTREGT, Maarten , TIEMEIJER, Lukas Frederik , KLAASSEN, Dirk
发明人： VAN DER WEL, Arnoud , VERTREGT, Maarten , TIEMEIJER, Lukas Frederik , KLAASSEN, Dirk
IPC分类号： H01L29/93 , H01L29/94
CPC分类号： H01L29/93 , H01L29/94
摘要： The present application relates to a circuit, in particular an analogue circuit and/or RF circuit, comprising at least one varactor device, wherein at least a bulk of the varactor device is electrically connected to at least one power source, wherein at least a drain of the varactor device is electrically connected to at least one alternate current power source, wherein at least a source of the varactor device is electrically connected to the at least one alternate current power source, and wherein at least a gate of the varactor device is electrically connected to at least one tuneable power source.
摘要翻译：本申请涉及一种包括至少一个变容二极管装置的电路，特别是模拟电路和/或RF电路，其中变容二极管装置的至少一部分电连接到至少一个电源，其中至少一个漏极所述变容二极管器件的至少一个电连接到至少一个交流电源，其中所述变容二极管器件的至少一个源电连接到所述至少一个交流电源，并且其中所述变容二极管器件的至少一个栅极是电连接到至少一个可调电源。

8. 发明申请

WO2003105229A3 RESISTOR NETWORK SUCH AS A RESISTOR LADDER NETWORK AND A METHOD FOR MANUFACTURING SUCH A RESISTOR NETWORK 审中-公开
公开(公告)号：WO2003105229A3
公开(公告)日：2003-12-18
申请号：PCT/IB2003/002192
申请日：2003-05-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TUINHOUT, Hans, P. , HOOGZAAD, Gian , VERTREGT, Maarten
发明人： TUINHOUT, Hans, P. , HOOGZAAD, Gian , VERTREGT, Maarten
IPC分类号： H01L27/08
摘要： The invention relates to a resistor network (2) such as a resistor ladder network, comprising at least a resistor body (4) which is provided with at least a column (6) of taps (8) situated between a first tap and a second tap, wherein, in use, at least two taps can be connected with respective first and second sources of reference input potentials, and wherein each tap of the at least one column of taps can be used for outputting an output potential via a contact area which is connected with the concerning tap, wherein the resistor body (4) comprises a multiple of resistor sub-bodies (5), wherein each resistor sub-body (5) is connected with a column (6) of taps (8), and wherein the only electrical connections between the resistor sub-bodies (5) are established by electrical connections via taps (8) connected with the resistor sub-bodies (5). Furthermore the invention relates to a method for manufacturing a resistor network (2) such as a resistor ladder network.

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