专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007011582A2 HIGH DENSITY NAND NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：高密度非易失性存储器件
公开(公告)号：WO2007011582A2
公开(公告)日：2007-01-25
申请号：PCT/US2006/026894
申请日：2006-07-12
申请人： MICRON TECHNOLOGY, INC. , BHATTACHARYYA, Arup
发明人： BHATTACHARYYA, Arup
IPC分类号： H01L27/115 , H01L21/8247 , H01L21/8246 , G11C16/04
CPC分类号： H01L29/792 , G11C16/0475 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/4232 , H01L29/42336 , H01L29/513 , H01L29/7881
摘要： Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non- volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate- stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or direct tunnel barriers of the floating node memory cells of embodiments of the present invention allow for low voltage tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The memory cell architecture also allows for improved high density memory devices or arrays with the utilization of reduced feature word lines and vertical select gates.
摘要翻译：描述了非易失性存储器装置和阵列，其利用具有频带工程栅极堆叠的双栅极（或背侧栅极）非易失性存储器单元，所述非易失性存储器单元放置在沟道区域之上或之下在前面 NAND存储器阵列架构中的侧边或背面电荷俘获栅极堆叠配置。具有本发明实施例的浮动节点存储器单元的不对称或直接隧道势垒的带隙工程栅极叠层允许低电压隧穿编程和利用电子和空穴的有效擦除，同时保持高电荷阻挡势垒和深度载流子俘获可以保持良好的电荷。存储器单元架构还允许利用减少的特征字线和垂直选择栅极改进高密度存储器件或阵列。

2. 发明申请

WO2008127293A3 MEMORY TRANSISTOR WITH NANODOT FLOATING GATE AND CARBON NANOTUBE CONTROL GATE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：WO2008127293A3
公开(公告)日：2008-10-23
申请号：PCT/US2007/022167
申请日：2007-10-17
申请人： MICRON TECHNOLOGY, INC. , BHATTACHARYYA, Arup , FARNWORTH, Warren, M. , FARRAR, Paul, A.
发明人： BHATTACHARYYA, Arup , FARNWORTH, Warren, M. , FARRAR, Paul, A.
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788 , G11C16/04 , H01L21/027 , H01L21/768 , H01L29/423 , H01L27/28 , H01L29/06 , H01L51/05 , H01L51/00 , H01L51/10 , G11C13/02
摘要： A nanodot nonvolatile memory element comprises a substrate (203) having a source (201) and a drain (202) region formed therein, and an insulating layer (204) formed on the substrate. The insulating layer contains a nanocrystalline floating gate (206) of approximately three -to six nanometers in diameter formed at a distance of approximately two to five nanometers from the substrate, and a carbon nanotube control gate (205) having a diameter of approximately six nanometers or less is formed at a distance of approximately 10-15 nanometers from the substrate. The manufacturing process uses a self -aligning chaperonin protein mask. Carbon nanotubes are used for the bitlines and the via connections to the source and drain.

3. 发明申请

WO2007070424A1 ENHANCED MULTI-BIT NON-VOLATILE MEMORY DEVICE WITH RESONANT TUNNEL BARRIER 审中-公开
标题翻译：带有谐波隧道屏障的增强型多位非易失性存储器件
公开(公告)号：WO2007070424A1
公开(公告)日：2007-06-21
申请号：PCT/US2006/047031
申请日：2006-12-08
申请人： MICRON TECHNOLOGY, INC. , BHATTACHARYYA, Arup
发明人： BHATTACHARYYA, Arup
IPC分类号： H01L21/28 , G11C16/04 , H01L29/423 , H01L29/51
CPC分类号： H01L21/28273 , G11C11/56 , G11C16/0466 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/792
摘要： A non-volatile memory cell uses a resonant tunnel barrier (600) that has an amorphous silicon and/or amorphous germanium layer (611) between two layers (610, 612)of either HfSiON or LaAlO 3 . A charge trapping layer (620) is formed over the tunnel barrier. A high-k charge blocking layer is formed over the charge trapping layer. A control gate (623) is formed over the charge blocking layer. Another embodiment forms a floating gate (620) over the tunnel barrier (600) that is comprised of two oxide layers (610, 612) with an amorphous layer (611) of silicon and/or germanium between the oxide layers.
摘要翻译：非易失性存储单元使用在HfSiON或LaAlO 3 3的两层（610,612）之间具有非晶硅和/或非晶锗层（611）的谐振隧道势垒（600）。电荷捕获层（620）形成在隧道势垒上。在电荷捕获层上形成高k电荷阻挡层。在电荷阻挡层上形成控制栅极（623）。另一个实施例在隧道势垒（600）上形成浮栅（620），该浮栅由两层氧化物层（610,612）和氧化物层之间的硅和/或锗的非晶层（611）组成。

4. 发明申请

WO2006125051A1 A NOVEL LOW POWER NON-VOLATILE MEMORY AND GATE STACK 审中-公开
标题翻译：一个新的低功耗非易失性存储器和栅极堆栈
公开(公告)号：WO2006125051A1
公开(公告)日：2006-11-23
申请号：PCT/US2006/019176
申请日：2006-05-17
申请人： MICRON TECHNOLOGY, INC. , BHATTACHARYYA, Arup
发明人： BHATTACHARYYA, Arup
IPC分类号： H01L29/788 , H01L29/792 , H01L29/51
CPC分类号： H01L29/513 , B82Y10/00 , H01L29/42332 , H01L29/7881 , H01L29/792 , Y10S438/954
摘要： Non- volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Memory cells of the present invention also allow multiple bit storage. These characteristics allow memory device embodiments of the present invention to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.
摘要翻译：描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的反向和正常模式浮动节点存储器单元中使用具有不对称隧道势垒的带隙工程化的栅极堆叠，其允许直接隧道编程和擦除，同时保持高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。低电压直接隧道编程和擦除能力降低了高能量载流子对栅极堆叠和晶格的损害，减少了写入疲劳和增强了器件寿命。低电压直接隧道编程和擦除功能还可以通过低电压设计和进一步的器件特性缩放来缩小尺寸。本发明的存储单元还允许多位存储。这些特征允许本发明的存储器件实施例在通用存储器的定义内操作，能够替代系统中的DRAM和ROM。

5. 发明申请

WO2005114742A2 SILICON ON INSULATOR READ-WRITE NON-VOLATILE MEMORY COMPRISING LATERAL THYRISTOR AND TRAPPING LAYER 审中-公开
标题翻译：绝缘子上的绝缘体读写式非易失性存储器，包括侧向电容器和捕获层
公开(公告)号：WO2005114742A2
公开(公告)日：2005-12-01
申请号：PCT/US2005/014433
申请日：2005-04-28
申请人： MICRON TECHNOLOGY, INC. , BHATTACHARYYA, Arup
发明人： BHATTACHARYYA, Arup
IPC分类号： H01L29/768
CPC分类号： H01L27/1027 , G11C11/39 , G11C16/349 , H01L21/28273 , H01L27/1203 , H01L29/66825 , H01L29/7436 , H01L29/749 , H01L29/87
摘要： Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell is formed in a floating substrate using Silicon-On-Insulator (SOI) technology. The cell preferably incorporates a lateral thyristor formed entirely in the floating substrate, and which is gated by a second word line. The cathode of the thyristor also comprises a source of an access transistor, whose drain is connected to the bit line of the device, and which is gated by a first word line. A trapping layer is built into the floating substrate, and when writing to the cell, pulses are added to cause holes to be trapped on the trapping layer for a logic state ‘1’ and to cause electrons to be trapped on the trapping layer for a logic state ‘0’. Trapping of charges on the trapping layer adds extra margin to the stored data states, prevents their degradation, and renders the cell non-volatile.
摘要翻译：本文公开了一种改进的基于晶闸管的存储单元。在一个实施例中，使用绝缘体上硅（SOI）技术在浮置衬底中形成电池。电池优选地包括完全在浮置衬底中形成的并由第二字线选通的横向晶闸管。晶闸管的阴极还包括存取晶体管的源极，其漏极连接到器件的位线，并且由第一字线选通。在浮置衬底中内置陷阱层，并且当写入单元时，添加脉冲以使空穴被捕获在捕获层上以达到逻辑状态'1'并且使电子被捕获在俘获层上以用于逻辑状态'0'。在陷阱层上捕获电荷对存储的数据状态增加了额外的余量，防止其退化，并使单元非易失性。

6. 发明申请

WO2009042028A2 LANTHANIDE DIELECTRIC WITH CONTROLLED INTERFACES 审中-公开
标题翻译：具有控制接口的LANTHANIDE电介质
公开(公告)号：WO2009042028A2
公开(公告)日：2009-04-02
申请号：PCT/US2008/010482
申请日：2008-09-08
申请人： MICRON TECHNOLOGY, INC. , BHATTACHARYYA, Arup
发明人： BHATTACHARYYA, Arup
IPC分类号： H01L21/336
CPC分类号： H01L21/3141 , H01G4/08 , H01L21/28194 , H01L21/316 , H01L28/40 , H01L29/513 , H01L29/517
摘要： Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.
摘要翻译：提供电介质的方法和装置。一个方法实施例包括在衬底上形成钝化层，其中钝化层含有硅，氧和氮的组成。该方法还包括在钝化层上形成镧系元素介电膜，并在镧系元素介电膜上形成封装层。

7. 发明申请

WO2009032606A2 THIN GATE STRUCTURE FOR MEMORY CELLS AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译：记忆细胞的薄栅结构及其形成方法
公开(公告)号：WO2009032606A2
公开(公告)日：2009-03-12
申请号：PCT/US2008/074248
申请日：2008-08-25
申请人： MICRON TECHNOLOGY, INC. , BHATTACHARYYA, Arup , DERDERIAN, Garo
发明人： BHATTACHARYYA, Arup , DERDERIAN, Garo
IPC分类号： H01L29/78 , H01L27/10 , G11C11/40
CPC分类号： H01L21/28273 , G11C2207/2245 , H01L21/28282 , H01L29/42324
摘要： Embodiments are described for reducing the programming voltage of a memory cell in a memory device. The memory cell includes a channel region extending between first and second diffusion regions formed in a substrate. A tunnel dielectric material is formed over the channel region. A storage medium is formed over the tunnel dielectric material to store electrical charge. The storage medium is disposed between a first interface material and a second interface material, each interface material provides a smoother interface between the storage medium and surrounding dielectric materials. A charge blocking material is formed over the storage medium, followed by a control gate material.
摘要翻译：描述了用于减小存储器件中的存储器单元的编程电压的实施例。存储器单元包括在形成于衬底中的第一和第二扩散区之间延伸的沟道区。隧道介电材料形成在沟道区上。存储介质形成在隧道介电材料上以存储电荷。存储介质设置在第一界面材料和第二界面材料之间，每个界面材料在存储介质和周围介电材料之间提供更平滑的界面。在存储介质上形成电荷阻挡材料，然后形成控制栅极材料。

8. 发明申请

WO2006057773A1 SCALABLE INTEGRATED LOGIC AND NON-VOLATILE MEMORY 审中-公开
标题翻译：可扩展的集成逻辑和非易失性存储器
公开(公告)号：WO2006057773A1
公开(公告)日：2006-06-01
申请号：PCT/US2005/039391
申请日：2005-11-01
申请人： MICRON TECHNOLOGY, INC. , BHATTACHARYYA, Arup
发明人： BHATTACHARYYA, Arup
IPC分类号： H01L29/423 , H01L21/28 , H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/4966 , H01L29/66825
摘要： A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. A compatible non-volatile memory transistor can be formed from this basic structure by adding a high-K dielectric constant film with an embedded metal nano-dot layer between the tunnel insulator and the gate stack.
摘要翻译：可扩展的逻辑晶体管具有用于漏极和源极的一对掺杂区域。栅极绝缘体层形成在衬底上并且在漏极和源极区域之间。栅层叠在两个金属氮化物层之间由诸如多晶硅或金属之类的栅极层形成。通过在隧道绝缘体和栅极堆叠之间添加具有嵌入金属纳米点层的高K介电常数膜，可以从该基本结构形成兼容的非易失性存储晶体管。

9. 发明申请

WO2006026159A1 INTEGRATED DRAM-NVRAM MULTI-LEVEL MEMORY 审中-公开
标题翻译：集成DRAM-NVRAM多级存储器
公开(公告)号：WO2006026159A1
公开(公告)日：2006-03-09
申请号：PCT/US2005/029150
申请日：2005-08-16
申请人： MICRO TECHNOLOGY, INC. , BHATTACHARYYA, Arup , FORBES, Leonard
发明人： BHATTACHARYYA, Arup , FORBES, Leonard
IPC分类号： G11C11/00
CPC分类号： G11C14/00 , G11C11/5621 , G11C11/5671 , G11C14/0018
摘要： An integrated DRAM-NVRAM (170, 171), multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate (120) floating plate (115, 116) device. The floating plate device (115, 116) provides enhanced charge storage for the DRAM part (104, 130, 101, 105, 131) of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate (100) with trenches that form pillars. A vertical wordline/gate (131, 130) on one side of a pillar is used to control the DRAM part (104, 130, 101, 105, 131, 103) of the cell. A vertical trapping layer (115, 116) on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate (120) is formed alongside the trapping layer and is shared with an adjacent floating plate device (115, 116).
摘要翻译：集成DRAM-NVRAM（170,171）的多电平存储单元由具有共享垂直栅极（120）浮置板（115,116）装置的垂直DRAM装置组成。浮置板装置（115,116）通过这两个功能之间的柱中的共享浮体为DRAM单元（104,130,101,105,131）提供增强的电荷存储。存储单元形成在具有形成支柱的沟槽的衬底（100）中。在柱的一侧上的垂直字线/栅极（131,130）用于控制单元的DRAM部分（104,130,101,105,131,103）。在柱的另一侧的垂直捕获层（115,116）存储一个或多个电荷作为浮置板装置的一部分，并且通过DRAM和浮置板装置之间的浮体增强DRAM功能。垂直NVRAM字线/控制栅极（120）与俘获层一起形成，并与相邻的浮置板装置（115,116）共享。

10. 发明申请

WO2009051944A2 MEMORY CELLS, ELECTRONIC SYSTEMS, METHODS OF FORMING MEMORY CELLS, AND METHODS OF PROGRAMMING MEMORY CELLS 审中-公开
标题翻译：记忆细胞，电子系统，形成记忆细胞的方法，以及编程记忆细胞的方法
公开(公告)号：WO2009051944A2
公开(公告)日：2009-04-23
申请号：PCT/US2008/077383
申请日：2008-09-23
申请人： MICRON TECHNOLOGY, INC.
发明人： MIN, Kyu, S. , BREWER, Rhett, T. , KRISHNAMOHAN, Tejas , GRAETTINGER, Thomas, M. , RAMASWANY, D., V., Nirmal , WEIMER, Ronald, A. , BHATTACHARYYA, Arup
IPC分类号： H01L27/115
CPC分类号： G11C16/0483 , B82Y10/00 , G11C11/5671 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , Y10S977/943
摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
摘要翻译：一些实施例包括具有垂直堆叠的电荷俘获区的存储器单元，所述电荷俘获区通过电介质材料彼此间隔开。介电材料可以包括高k材料。一个或多个电荷俘获区可以包括金属材料。这种金属材料可以作为多个离散的孤立岛例如纳米点存在。一些实施例包括形成存储器单元的方法，其中两个电荷俘获区域形成在隧道电介质上方，其中区域相对于彼此垂直移位，并且最靠近隧道电介质的区域具有比另一个区域更深的陷阱。一些实施例包括包含存储单元的电子系统一些实施例包括对具有垂直堆叠的电荷俘获区的存储器单元进行编程的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式