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1. 发明申请

WO2012105084A1 MEMORY SYSTEM IN WHICH EXTENDED FUNCTION CAN EASILY BE SET 审中-公开
标题翻译：可以轻松设置扩展功能的记忆系统
公开(公告)号：WO2012105084A1
公开(公告)日：2012-08-09
申请号：PCT/JP2011/071776
申请日：2011-09-16
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa , SAKAMOTO, Hiroyuki
发明人： FUJIMOTO, Akihisa , SAKAMOTO, Hiroyuki
IPC分类号： G11C5/00 , G06F13/38
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F9/30134 , G06F12/00 , G06F12/0238 , G11C5/00
摘要： According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device (18), a control section (11a), a memory (14, 15), an extended function section (19), and an extension register. The extended function section (19) is controlled by the control section (11a). The extension register is provided on the memory (14, 15) or on the control section (11a). A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.
摘要翻译：根据一个实施例，诸如SDIO卡的存储器系统包括非易失性半导体存储器件（18），控制部分（11a），存储器（14,15），扩展功能部分（19）和扩展寄存器。扩展功能部（19）由控制部（11a）控制。扩展寄存器设置在存储器（14,15）或控制部分（11a）上。第一个命令以给定的数据长度为单位从扩展寄存器读取数据。第二个命令以给定的数据长度为单位将数据写入扩展寄存器。扩展寄存器包括第一区域和与第一区域不同的第二区域，被配置为指定扩展功能和可控驱动器的类型的信息，以及指示扩展功能被分配的地点的地址信息，扩展寄存器被记录在第一区域中，第二区域包括扩展功能。

2. 发明申请

WO2008156213A1 MEMORY DEVICE, ELECTRONIC DEVICE, AND HOST APPARATUS 审中-公开
标题翻译：存储装置，电子装置和主机装置
公开(公告)号：WO2008156213A1
公开(公告)日：2008-12-24
申请号：PCT/JP2008/061602
申请日：2008-06-19
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa , SAKAMOTO, Hiroyuki
发明人： FUJIMOTO, Akihisa , SAKAMOTO, Hiroyuki
IPC分类号： G06K17/00 , G06F3/08 , G06F12/06
CPC分类号： G06F12/0246 , G06F9/4401
摘要： A memory device (11) includes a semiconductor memory (11c) and a controller (11a). The semiconductor memory (11c) includes a first storage area (11c1) and a second storage area (11c2). The controller (11a) controls the semiconductor memory (11c). The memory device (11) is capable of having a first state which is accessible to the first storage area (11c1) and a second state in which data is readable from the second storage area (11c2). The controller (11a) is configured to recognize a first command, a second command, and a third command. The first command transfers the memory device (11) to the first state after the memory device is turned on. The second command transfers the memory device (11) from the first state to the second state. The third command transfers the memory device (11) to the second state without passing through the first state after the memory device is turned on.
摘要翻译：存储器件（11）包括半导体存储器（11c）和控制器（11a）。半导体存储器（11c）包括第一存储区域（11c1）和第二存储区域（11c2）。控制器（11a）控制半导体存储器（11c）。存储装置（11）能够具有第一存储区域（11c1）可访问的第一状态和从第二存储区域（11c2）读取数据的第二状态。控制器（11a）被配置为识别第一命令，第二命令和第三命令。在存储器件接通之后，第一命令将存储器件（11）传送到第一状态。第二命令将存储器件（11）从第一状态传送到第二状态。在存储器件接通之后，第三命令将存储器件（11）传送到第二状态而不经过第一状态。

3. 发明申请

WO2010067899A1 MEMORY DEVICE AND CONTROLLING METHOD OF THE SAME 审中-公开
标题翻译：存储器件及其控制方法
公开(公告)号：WO2010067899A1
公开(公告)日：2010-06-17
申请号：PCT/JP2009/071069
申请日：2009-12-11
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa
发明人： FUJIMOTO, Akihisa
IPC分类号： G06F12/00 , G06K19/07
CPC分类号： G06F12/0246 , G06F2212/7202
摘要： A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.
摘要翻译：存储器装置包括具有存储区域的存储器，并且控制器具有第一模式和第二模式。在接收到写入数据时，控制器在管理写入数据的逻辑地址和存储对应写入数据的存储器区域之间的对应关系的同时，将数据写入存储器区域。多个存储区域构成管理单元。第一模式中的控制器能够在相应存储区域中写入数据片，并且被配置为将数据保存在包含要更新的数据的一个管理单元中的存储器区域中。第二模式中的控制器以数据数据的逻辑地址的升序将数据中的数据写入到包含更新数据的一个管理单元的存储器区域中的数据无效。

4. 发明申请

WO2006070906A1 CARD AND HOST APPARATUS 审中-公开
标题翻译：卡和主机
公开(公告)号：WO2006070906A1
公开(公告)日：2006-07-06
申请号：PCT/JP2005/024205
申请日：2005-12-26
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa
发明人： FUJIMOTO, Akihisa
IPC分类号： G06K17/00 , B42D15/10 , G06F3/08 , G06K19/07
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/3203 , G06F1/3228 , G06F1/325 , G06F1/3281 , G06F3/0604 , G06F3/0619 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/4081 , G06K7/0008 , G06K7/0069 , G06K19/07732
摘要： A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.
摘要翻译：插入具有非易失性半导体存储器的卡的主机装置向卡发出检查命令。检查命令指示发送关于卡是否支持终止处理的信息，其中卡转移到准备停止从主机设备供电的状态。

5. 发明申请

WO2011093517A1 MEMORY DEVICE AND HOST DEVICE 审中-公开
标题翻译：存储器件和主机器件
公开(公告)号：WO2011093517A1
公开(公告)日：2011-08-04
申请号：PCT/JP2011/052189
申请日：2011-01-27
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa
发明人： FUJIMOTO, Akihisa
IPC分类号： G06F12/00 , G06F3/08 , G06F13/38 , G06K17/00 , G06K19/07
CPC分类号： G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06K7/10297 , G06K7/10861
摘要： According to one embodiment, a controller which controls a memory receives data items, and has a random write mode and a sequential write mode to which it transitions when receiving a start command. The controller in the sequential write mode recognizes a control command, and identifies one of data streams partially formed by a data item through the control command or a logical address. It also prepares free unit areas comprising the storage areas for respective data streams, and writes the data items in successive storage areas in a corresponding unit area in an order identical to addresses of the data items. When the controller receives an end command, it performs end processing on a unit area for a corresponding data stream. The controller in the sequential write mode transitions to the random write mode when completing the end processing to all data streams or detects a random write request.
摘要翻译：根据一个实施例，控制存储器的控制器接收数据项，并且具有随机写入模式和顺序写入模式，当接收到开始命令时，该写入模式和顺序写入模式转换到该模式。顺序写入模式下的控制器识别控制命令，并通过控制命令或逻辑地址识别由数据项部分形成的数据流之一。它还准备包括用于相应数据流的存储区域的空闲单元区域，并且以与数据项的地址相同的顺序将数据项写入相应单元区域中的连续存储区域中。当控制器接收到结束命令时，它对相应数据流的单位区域执行结束处理。当完成对所有数据流的结束处理或检测随机写入请求时，顺序写入模式中的控制器转换到随机写入模式。

6. 发明申请

WO2011074708A1 SEMICONDUCTOR SYSTEM, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE INITIALIZING METHOD 审中-公开
标题翻译：半导体系统，半导体器件和电子器件初始化方法
公开(公告)号：WO2011074708A1
公开(公告)日：2011-06-23
申请号：PCT/JP2010/073469
申请日：2010-12-17
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa
发明人： FUJIMOTO, Akihisa
IPC分类号： G06F1/24
CPC分类号： G06F9/4405 , G06F1/26 , G06F1/266 , G06F1/3287 , G06F13/00 , Y02D10/171
摘要： According to one embodiment of the present disclosure, a semiconductor system may be disclosed. The semiconductor system according to the one embodiment may include, for example, a plurality of electronic devices and a host apparatus. The host apparatus may simultaneously initialize the plurality of electronic devices in units of group.
摘要翻译：根据本公开的一个实施例，可以公开半导体系统。根据一个实施例的半导体系统可以包括例如多个电子设备和主机设备。主机装置可以以组为单位同时初始化多个电子装置。

7. 发明申请

WO2009116196A1 MEMORY DEVICE, HOST DEVICE, MEMORY SYSTEM5 MEMORY DEVICE CONTROL METHOD, HOST DEVICE CONTROL METHOD AND MEMORY SYSTEM CONTROL METHOD 审中-公开
标题翻译：存储器件，主机器件，存储器系统5存储器件控制方法，主机器件控制方法和存储器系统控制方法
公开(公告)号：WO2009116196A1
公开(公告)日：2009-09-24
申请号：PCT/JP2008/066618
申请日：2008-09-09
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa
发明人： FUJIMOTO, Akihisa
IPC分类号： G06F12/16 , G06K17/00 , G06K19/07
CPC分类号： G06F1/266 , G06K19/07
摘要： A memory card 100 having a NAND type flash memory connectable to a host device 200, capable of transmitting/receiving a signal to/from the host device 200 at a first voltage (3.3 V) or a second voltage (1.8 V) and safely changing a signal voltage of a transmission/reception signal that mutually checks a signal voltage through handshake processing with the host device 200 when the signal voltage is switched.
摘要翻译：存储卡100，其具有可连接到主机设备200的NAND型闪存，能够以第一电压（3.3V）或第二电压（1.8V）向主机设备200发送/接收信号，并且安全地改变当切换信号电压时，通过与主机装置200的握手处理相互检查信号电压的发送/接收信号的信号电压。

8. 发明申请

WO2009116195A1 DATA UPDATING METHOD, MEMORY SYSTEM AND MEMORY DEVICE 审中-公开
标题翻译：数据更新方法，存储器系统和存储器件
公开(公告)号：WO2009116195A1
公开(公告)日：2009-09-24
申请号：PCT/JP2008/066617
申请日：2008-09-09
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa
发明人： FUJIMOTO, Akihisa
IPC分类号： G06F12/00 , G06F9/445 , G06F11/00 , G06F12/02 , G06K19/07
CPC分类号： G06F12/1433 , G06F8/65 , G06F9/4401 , G06F11/1417 , G06F11/1433 , G06F12/0246 , G06F2212/2022 , G06F2212/7206 , G06F2212/7209
摘要： A data updating method, a memory system and a memory device in which the memory device is connectable to a host device and has a memory section and a memory controller, the memory section consists of a first memory section which can be divided into partitions having multiple different attributes, and a work space which is managed by the memory controller, and the method of updating data which is stored in the memory device uses one of the writing methods which has been selected from among multiple different writing methods of writing data into the partition, depending on the attribute of the partition, to perform an updating process, and can securely update the data.
摘要翻译：一种数据更新方法，存储器系统和存储器件，其中存储器件可连接到主机设备并且具有存储器部分和存储器控制器，所述存储部分包括第一存储器部分，其可被划分成具有多个不同的属性和由存储器控制器管理的工作空间，并且更新存储在存储装置中的数据的更新方法使用从将数据写入分区的多种不同写入方法中选择的写入方法之一，取决于分区的属性，执行更新过程，并可以安全地更新数据。

9. 发明申请

WO2006051629A1 MEMORY CARD HAVING MEMORY ELEMENT AND CARD CONTROLLER THEREOF 审中-公开
标题翻译：具有记忆元素和卡控制器的记忆卡
公开(公告)号：WO2006051629A1
公开(公告)日：2006-05-18
申请号：PCT/JP2005/009596
申请日：2005-05-19
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa
发明人： FUJIMOTO, Akihisa
IPC分类号： G06F13/32
CPC分类号： G06F13/385
摘要： A card controller is built in a memory card capable of being loaded in a host device which can detect interrupt. The interface unit receives and decodes a command from the host device, sends a response or data to the host device, and receives data therefrom. The read/write control unit executes writing and reading of the data in accordance with a result of decoding the command. The error detecting unit detects whether an error occurred in the sending and receiving of the data executed by the interface unit, and in at least one of the writing and reading of the data executed by the read/write control unit. The signal processing unit outputs an interrupt signal to the host device via the interface unit during a period in which the interface unit does not execute sending or receiving the data, when the error detecting unit detects the occurrence of the error.
摘要翻译：卡控制器内置在能够被加载到可以检测中断的主机设备中的存储卡中。接口单元接收并解码来自主机设备的命令，向主机设备发送响应或数据，并从其接收数据。读/写控制单元根据解码命令的结果执行数据的写入和读取。错误检测单元检测在由接口单元执行的数据的发送和接收中以及由读/写控制单元执行的数据的写入和读取中的至少一个中是否发生错误。当错误检测单元检测到错误的发生时，信号处理单元在接口单元不执行发送或接收数据的时段期间经由接口单元向主机设备输出中断信号。

10. 发明申请

WO2006006694A1 STORAGE DEVICE AND HOST APPARATUS 审中-公开
标题翻译：存储设备和主机设备
公开(公告)号：WO2006006694A1
公开(公告)日：2006-01-19
申请号：PCT/JP2005/013104
申请日：2005-07-08
申请人： KABUSHIKI KAISHA TOSHIBA , FUJIMOTO, Akihisa
发明人： FUJIMOTO, Akihisa
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/061 , G06F3/0632 , G06F3/0634 , G06F3/0679 , G06F12/0246 , G06F13/385 , G06F2206/1014 , G11C16/20
摘要： A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.
摘要翻译：存储装置包括存储数据的半导体存储器。控制器指示根据控制器接收的请求将数据写入半导体存储器。寄存器保存性能等级信息，显示允许存储设备显示存储设备支持的最佳性能所需的一个性能等级，根据性能指定的性能等级。

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