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1. 发明申请

WO0201571A3 SHIELDED BIT LINE ARCHITECTURE FOR MEMORY ARRAYS 审中-公开
标题翻译：存储阵列的屏蔽位线结构
公开(公告)号：WO0201571A3
公开(公告)日：2002-04-18
申请号：PCT/US0120199
申请日：2001-06-25
申请人： INFINEON TECHNOLOGIES CORP , INFINEON TECHNOLOGIES RICHMOND
发明人： VOLLRATH JOERG , FERA MICHAEL , MOORE PHILIP
IPC分类号： G11C5/06 , G11C7/18 , G11C17/18 , G11C11/4097
CPC分类号： G11C5/063 , G11C7/18
摘要： An architecture for bitlines in memory arrays, in accordance with the invention, includes a plurality of memory cells (114) disposed in an array. A plurality of bitlines (112) are included for reading and writing data to and from the memory cells. The plurality of bitlines include a first group of bitlines (1121) and a second group of bitlines (1122). Each bitline of the first group is interposed between bitlines of the second group, and each bitline of the second group is interposed between bitlines of the first group. The first group of bitlines are active when the second group of bitlines are inactive, and the second group of bitlines are active when the first group of bitlines are inactive such that adjacent inactive bitlines provide a shield to prevent cross-coupling between active bitlines.
摘要翻译：根据本发明，用于存储器阵列中的位线的架构包括设置在阵列中的多个存储器单元（114）。包括多个位线（112）以用于从存储器单元读取数据和向存储器单元写入数据。多个位线包括第一组位线（1121）和第二组位线（1122）。第一组的各位线介于第二组的位线之间，并且第二组的各位线介于第一组的位线之间。当第二组位线不活动时，第一组位线有效，而当第一组位线不活动时，第二组位线有效，使得相邻的非有效位线提供屏蔽以防止有效位线之间的交叉耦合。

2. 发明申请

WO0142803A3 BIT FAIL MAP COMPRESSION WITH FAIL SIGNATURE ANALYSIS 审中-公开
标题翻译：位失败地图压缩与失败签名分析
公开(公告)号：WO0142803A3
公开(公告)日：2001-11-08
申请号：PCT/US0032847
申请日：2000-12-05
申请人： INFINEON TECHNOLOGIES CORP
发明人： VOLLRATH JOERG , HLADSCHIK THOMAS , ANDREAS ZSCHUNKE , OSWALD PETER , LEDERER ULF , HAROLD RAUSCH
IPC分类号： G01R31/3193 , G11C29/00 , G11C29/56 , G06F11/20
CPC分类号： G11C29/72 , G01R31/31935 , G11C29/56
摘要： A method for providing a compressed bit fail map, in accordance with the invention includes the steps of testing a semiconductor device to determine failed devices (802) and transferring failure information to display a compressed bit map by designating areas of the bit map for corresponding failure locations on the semiconductor device (806). Failure classification is provided by designating shapes and dimensions of fail areas in the designated areas of the bit map such that the fail area shapes and dimensions indicate a fail type (808).
摘要翻译：根据本发明的用于提供压缩比特失败映射的方法包括以下步骤：测试半导体器件以确定故障设备（802）并且通过指定用于相应故障的位图的区域来传送故障信息以显示压缩位图半导体器件（806）上的位置。通过在位图的指定区域中指定失效区域的形状和尺寸来提供故障分类，使得故障区域形状和尺寸表示故障类型（808）。

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