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1. 发明申请

WO1994018670A1 SYNCHRONOUS READ CHANNEL 审中-公开
标题翻译：同步读通道
公开(公告)号：WO1994018670A1
公开(公告)日：1994-08-18
申请号：PCT/US1994001084
申请日：1994-01-31
申请人： CIRRUS LOGIC, INC.
发明人： CIRRUS LOGIC, INC. , BEHRENS, Richard, T. , ANDERSON, Kent, D. , ARMSTRONG, Alan , DUDLEY, Trent , FOLAND, Bill , GLOVER, Neal , KING, Larry
IPC分类号： G11B05/09
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control (32), timing recovery (34), sequence detection (40), RLL (1, 7) encoding (48) and RLL (1, 7) decoding (28), and channel quality measurement (46) is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection (40). These characteristics, together with error-tolerant sync mark detection (26) and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.
摘要翻译：具有提供数字增益控制（32），定时恢复（34），序列检测（40），RLL（1,7）编码（48）和RLL（1,7）的单芯片集成电路数字部分的同步读通道，解码（28）和信道质量测量（46）。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测提供解码数据的能力（40）。这些特性以及容错同步标记检测（26）以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略来最大限度地提高数据恢复的可能性。

2. 发明申请

WO1993019418A1 METHOD AND APPARATUS FOR REDUCED-COMPLEXITY VITERBI-TYPE SEQUENCE DETECTORS 审中-公开
标题翻译：减少复合型VITERBI型序列检测器的方法和装置
公开(公告)号：WO1993019418A1
公开(公告)日：1993-09-30
申请号：PCT/US1993002241
申请日：1993-03-11
申请人： CIRRUS LOGIC, INC.
发明人： CIRRUS LOGIC, INC. , BEHRENS, Richard, T. , ANDERSON, Kent, D. , GLOVER, Neal
IPC分类号： G06F11/10
CPC分类号： G11B20/1426 , G11B20/1833 , H03M13/41 , H03M13/4107 , H04L25/4906 , H04L25/497
摘要： In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. An ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module. Groups of sequence-model states may be chosen to share an ACS module without significant loss in performance as compared to the original, unreduced Viterbi demodulator.
摘要翻译：在使用加法，比较，选择（ACS）方法实现的典型维特比解调器中，预期采样序列模型中的每个状态与硬件模块相关联，以执行向路径误差度量添加新的分支误差度量的功能，比较路径误差度量，并选择具有最低路径错误度量的路径。 ACS模块可以具有与其动态相关联的两个或更多个序列模型状态，使得在某些时候一个序列模型状态与其相关联，并且在其他时间，另一个序列模型状态与其相关联。这减少了所需的ACS模块的数量，并且还降低了解调器的路径存储器的大小/复杂性，这些存储器必须存储每个ACS模块的一个路径。与原始的未导通的维特比解调器相比，可以选择一组序列模型状态来共享ACS模块，而没有显着的性能损失。

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