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1. 发明申请

WO2004049432A3 SEALING POROUS STRUCTURES 审中-公开
标题翻译：密封多孔结构
公开(公告)号：WO2004049432A3
公开(公告)日：2004-12-02
申请号：PCT/US0340061
申请日：2003-11-21
申请人： ASM INC , ASM INT
发明人： RAAIJMAKERS IVO , SOININEN PEKKA J , GRANNEMAN ERNST , HAUKKA SUVI , ELERS KAI-ERIK , TUOMINEN MARCO , SPREY HESSEL , TERHORST HERBERT , HENDRIKS MENSO
IPC分类号： H01L21/285 , H01L21/768 , H01L23/00 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/28562 , H01L21/7681 , H01L21/76814 , H01L21/7682 , H01L21/76825 , H01L21/76828 , H01L21/76831 , H01L21/76844 , H01L21/76864 , H01L21/76873 , H01L23/5226 , H01L23/53238 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality. An alternating process can also be arranged by selection of pulse separation and/or pulse duration to achieve reduced conformality relative to a self-saturating, self-limiting atomic layer deposition (ALD) process. In still another arrangement, layers with anisotropic pore structures can be sealed by selectively melting upper surfaces. Blocking is followed by a self-limiting, self-saturating atomic layer deposition (ALD) reactions without significantly filling the pores.
摘要翻译：提供了用于集成电路中的双镶嵌结构的保形衬里的方法和结构，特别是在多孔材料中形成的开口。沟槽和接触通孔形成在绝缘层中。沟槽和通孔的侧壁上的孔堵塞，然后将结构暴露于交替的化学物质以形成所需衬里材料的单层。在示例性工艺流程中，密封层的化学或物理气相沉积（CVD或PVD）由于不完美的共形性而堵塞孔。也可以通过选择脉冲分离和/或脉冲持续时间来布置交替过程，以相对于自饱和的自限制性原子层沉积（ALD）工艺实现降低的共形。在另一种布置中，可以通过选择性地熔化上表面来密封具有各向异性孔结构的层。之后是自限制的，自饱和的原子层沉积（ALD）反应而没有显着填充孔隙。

2. 发明申请

WO02067319A8 COPPER INTERCONNECT STRUCTURE HAVING DIFFUSION BARRIER 审中-公开
标题翻译：具有扩散障碍物的铜互连结构
公开(公告)号：WO02067319A8
公开(公告)日：2004-02-26
申请号：PCT/US0147592
申请日：2001-12-05
申请人： ASM INT , KIM KI-BUM , RAAIJMAKERS IVO , SOININEN PEKKA J
发明人： KIM KI-BUM , RAAIJMAKERS IVO , SOININEN PEKKA J
IPC分类号： C23C16/20 , C23C16/34 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/76846 , H01L21/28562 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film (32) combined with an Al intermediate layer (34) is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.
摘要翻译：本发明提供一种制造半导体器件的方法，其可以通过铜互连促进半导体器件的商业化。在金属互连线制造的过程中，将与Al中间层（34）组合的TiN薄膜（32）用作沟槽或通孔壁上的扩散阻挡层。为了形成，Al沉积在TiN薄膜上，随后铜填充沟槽。 Al扩散到TiN层并与氧或氮反应，这将有效地吸收晶界，从而阻止铜的扩散。

3. 发明申请

WO9923691A3 IMPROVED LOW MASS WAFER SUPPORT SYSTEM 审中-公开
标题翻译：改进的低质量晶圆支持系统
公开(公告)号：WO9923691A3
公开(公告)日：1999-08-05
申请号：PCT/US9823324
申请日：1998-11-02
申请人： ASM INC
发明人： GOODMAN MATTHEW G , RAAIJMAKERS IVO , JACOBS LOREN R , VAN BILSEN FRANCISCUS B M , MEYER MICHAEL J , BARRETT ERIC ALAN
IPC分类号： H01L21/683 , C23C16/458 , C23C16/48 , H01L21/205 , H01L21/26 , H01L21/687 , H01L21/00
CPC分类号： H01L21/68735 , C23C16/4581 , C23C16/4585 , C23C16/481 , H01L21/68721 , H01L21/68728 , H01L21/68785
摘要： Improvements in the design of a low mass wafer holder are disclosed. The improvements include the use of peripherally located, integral lips to space a wafer or other substrate above the base plate of the wafer holder. A uniform gap is thus provided between the wafer and the base plate, such as will temper rapid heat exchanges, allow gas to flow between the wafer and wafer holder during wafer pick-up, and keep the wafer holder thermally coupled with the wafer. At the same time, thermal disturbance from lip contact with the wafer is reduced. Gas flow during pick-up can be provided through radial channels in a wafer holder upper surface, or through backside gas passages. A thicker ring is provided at the wafer holder perimeter, and is provided in some embodiments as an independent piece to accommodate stresses accompanying thermal gradients. A self-centering mechanism is provided to keep the wafer holder centered relative to a spider which is subject to differential thermal expansion.
摘要翻译：公开了一种小质量晶片支架设计的改进。这些改进包括使用外围定位的整体唇缘来将晶片或晶片支架的基板上方的其他衬底间隔开。因此在晶片和基板之间提供了均匀的间隙，例如将调节快速热交换，允许气体在晶片拾取期间在晶片和晶片保持器之间流动，并保持晶片保持器与晶片热耦合。同时，减少了与晶片唇缘接触的热干扰。拾取期间的气流可以通过晶片支架上表面中的径向通道或通过背侧气体通道提供。在晶片支架周边处提供较厚的环，并且在一些实施例中设置为独立的部件以适应伴随着热梯度的应力。提供自定心机构以保持晶片支架相对于受到不同热膨胀的蜘蛛而居中。

4. 发明申请

WO0117692A9 IMPROVED APPARATUS AND METHOD FOR GROWTH OF A THIN FILM 审中-公开
标题翻译：改进的薄膜生长装置和方法
公开(公告)号：WO0117692A9
公开(公告)日：2002-10-03
申请号：PCT/US0024586
申请日：2000-09-08
申请人： ASM INC
发明人： RAAIJMAKERS IVO
IPC分类号： C23C16/44 , C23C16/452 , C23C16/455 , H01L21/205 , B05C11/00 , H05H1/10
CPC分类号： C23C16/45544 , C23C16/452 , C23C16/45521 , C23C16/45536 , C23C16/45542 , C30B25/14 , C30B29/38 , H01J37/3244 , Y10T117/10
摘要： An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas (C, D) delivery of sequential pulses of reactants (A, B) to the substrate surfaces. (5) At least one of the reactants (A, B) comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas (4, 13) for reaction at a substrate surfaces. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants (A, B) in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface (5).
摘要翻译：一种用于衬底层沉积的改进的装置和方法，其中衬底层通过载气（C，D）将反应物（A，B）的顺序脉冲传送到衬底表面而生长。（5）至少一种反应物（A，B）包括激发物质，例如自由基。在一个具体实施方案中，本发明的装置在载气（4,13）流中提供反应物的顺序重复脉冲，用于在基底表面反应。反应物脉冲以足够的中间延迟时间递送，以使在气相中的相邻脉冲中的反应物（A，B）之间的不希望的反应最小化，或者在衬底表面（5）上不期望的不受控制的反应。

5. 发明申请

WO0003467A2 WAFER CARRIER AND METHOD FOR HANDLING OF WAFERS WITH MINIMAL CONTACT 审中-公开
标题翻译：具有最小接触面的波浪器和波浪方式
公开(公告)号：WO0003467A2
公开(公告)日：2000-01-20
申请号：PCT/US9915593
申请日：1999-07-08
申请人： ASM INC
发明人： CARR PAUL R , JACOBSON PAUL T , KUSBEL JAMES F , ROUNDY JAMES S , AGGARWAL RAVINDER K , RAAIJMAKERS IVO , LENZ ROD , RAJBHARTI NILESH
IPC分类号： B65G49/07 , H01L21/673 , H01L21/677 , H01L21/687 , H02G1/00
CPC分类号： H01L21/68735 , H01L21/67346 , H01L21/67778 , H01L21/68721 , H01L21/68728 , H01L21/68764 , H01L21/68771 , Y10S414/137 , Y10S414/141
摘要： Disclosed is a carrier (10) comprising three support elements (50) connected by an underlying frame (15). The periphery of a wafer (45) rests upon the support elements (50). Also disclosed is a wafer handler (25) with a plurality of arms (100). Spacers (85) space the carrier (10) above a base plate (90) associated with a station in a wafer handling area. An arm (100) slides beneath the frame (15) and between the spacers (85), but the handler (25) does not contact the wafer (45). A method of using the handler (25) and carrier (10) is provided where the handler (55) lifts and rotates the carrier (10) with the wafer (45) through various stations (112, 125, 126 and 130) in a wafer handling area (95). A control device (33) reduces the handler speed only at critical points of the processing cycle. The handler (55) is capable of moving a plurality of carriers (10) and wafers (45) simultaneously.
摘要翻译：公开了一种载体（10），其包括由下面的框架（15）连接的三个支撑元件（50）。晶片（45）的周边位于支撑元件（50）上。还公开了具有多个臂（100）的晶片处理器（25）。间隔件（85）使载体（10）在与晶片处理区域中的站相关联的基板（90）上方空间。臂（100）在框架（15）下方和间隔件（85）之间滑动，但是处理器（25）不接触晶片（45）。提供了一种使用处理器（25）和托架（10）的方法，其中处理器（55）通过各种工作站（112,125,126和130）提升并旋转载体（10）与晶片（45）晶片处理区域（95）。控制装置（33）仅在处理周期的关键点降低处理器速度。处理器（55）能够同时移动多个载体（10）和晶片（45）。

6. 发明申请

WO9923276A8 LONG LIFE HIGH TEMPERATURE PROCESS CHAMBER 审中-公开
标题翻译：长寿命高温加工室
公开(公告)号：WO9923276A8
公开(公告)日：1999-09-16
申请号：PCT/US9823205
申请日：1998-11-02
申请人： ASM INC
发明人： WENGERT JOHN F , RAAIJMAKERS IVO , HALPIN MIKE , JACOBS LOREN , MEYER MICHAEL J , VAN BILSEN FRANK , GOODMAN MATT , BARRETT ERIC , WOOD ERIC , SAMUELS BLAKE
IPC分类号： C23C16/44 , C23C16/48 , G01K1/12 , H01L21/00 , H01L21/205
CPC分类号： H01L21/67115 , C23C16/4401 , C23C16/481 , G01K1/12 , G01K7/04
摘要： A generally horizontally-oriented quartz CVD chamber (10) is disclosed with front and rear chamber divider plates (16, 18) adjacent a centrally positioned susceptor (20) and surrounding temperature control ring (22) which divide the chamber into upper and lower regions. Improvement to the lifetime of CVD process components and related throughput improvements are disclosed. A getter plate (30) for attracting some of the unused reactant gas is positioned downstream from the susceptor extending generally parallel to and spaced between the divider plate and the upper chamber wall. This getter plate also minimizes deposition on the chamber walls and improves the efficiency of a cleaning step. Reradiating elements are also located adjacent side walls of the chamber to heat cooler chamber wall areas. The getter plate and the reradiating elements plus the susceptor and surrounding ring are all made of solid chemical vapor deposited SiC to improve the life of the chamber. Also, thermocouples (34) adjacent the susceptor are provided with SiC sheaths to enable the thermocouples to withstand more process cycles than that of quartz sheaths. SiC shields may be provided on quartz components throughout the chamber to protect the quartz from devitrification. Throughput is improved by both reducing down time and reducing the cleaning step time of the process cycle.
摘要翻译：公开了一种通常水平定向的石英CVD室（10），其具有邻近中心定位的基座（20）和周围的温度控制环（22）的前室分隔板（16）和后室分隔板（18），其将室分成上部区域和下部区域。公开了改善CVD工艺部件的寿命和相关的产量改进。用于吸引一些未使用的反应气体的吸气板（30）位于基座平行于分隔板和上腔室壁并在其间隔开的基座下游。该吸气板还减少了室壁上的沉积并提高了清洁步骤的效率。再辐射元件也位于腔室的侧壁附近以加热冷却器腔室壁区域。吸气板和再辐射元件加上感受器和周围环都是由固体化学气相沉积SiC制成的，以改善腔室的寿命。而且，与基座相邻的热电偶（34）设置有SiC护套，以使热电偶能够承受比石英护套更多的工艺循环。可以在整个腔室的石英部件上设置SiC屏蔽以保护石英不发生反玻璃化。吞吐量通过减少停机时间和缩短工艺循环的清洁步骤时间而得到改善。

7. 发明申请

WO0245167A2 THIN FILMS FOR MAGNETIC DEVICES 审中-公开
标题翻译：薄膜用于磁性装置
公开(公告)号：WO0245167A2
公开(公告)日：2002-06-06
申请号：PCT/US0144350
申请日：2001-11-26
申请人： ASM MICROCHEMISTRY OY , ASM INC , HUJANEN JUHA , RAAIJMAKERS IVO
发明人： HUJANEN JUHA , RAAIJMAKERS IVO
IPC分类号： G01R33/09 , C23C16/40 , G11B5/39 , H01F10/16 , H01F10/32 , H01F41/22 , H01F41/30 , H01F41/32 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L29/82 , H01L43/08 , H01L43/12 , H01L27/00
CPC分类号： H01F10/3231 , B82Y10/00 , B82Y25/00 , B82Y40/00 , G11B5/3903 , G11B5/3909 , G11B2005/3996 , H01F10/3254 , H01F41/22 , H01F41/307 , H01L43/12
摘要： Methods are provided for forming uniformly thin layers in magnetic devices. Atomic layer deposition (ALD) can produce layers that are uniformly thick on an atomic scale. Magnetic tunnel junction dielectrics, for example, can be provided with perfect uniformity in thickness of 4 monolayers or less. Furthermore, conductive layers, including magnetic 12, 16 and non-magnetic layers 14, can be provided by ALD without spiking and other non-uniformity problems. The disclosed methods include forming metal oxide layers by multiple cycles of ALD and subsequently reducing the oxides to metal. The oxides tend to maintain more stable interfaces during formation.
摘要翻译：提供了用于在磁性装置中形成均匀薄层的方法。原子层沉积（ALD）可以产生原子尺度均匀厚的层。例如，磁性隧道结电介质可以提供4个单层或更小厚度的完美均匀度。此外，包括磁性12,16和非磁性层14的导电层可以由ALD提供，而不会引起尖峰和其他不均匀性问题。所公开的方法包括通过多次ALD形成金属氧化物层，随后将氧化物还原成金属。氧化物在形成过程中往往保持更稳定的界面。

8. 发明申请

WO2004084268A3 EPITAXIAL SEMICONDUCTOR DEPOSITION METHODS AND STRUCTURES 审中-公开
标题翻译：外延半导体沉积方法和结构
公开(公告)号：WO2004084268A3
公开(公告)日：2005-06-16
申请号：PCT/US2004007564
申请日：2004-03-12
申请人： ASM INC , BRABANT PAUL D , ITALIANO JOSEPH P , ARENA CHANTAL J , TOMASINI PIERRE , RAAIJMAKERS IVO , BAUER MATTHIAS
发明人： BRABANT PAUL D , ITALIANO JOSEPH P , ARENA CHANTAL J , TOMASINI PIERRE , RAAIJMAKERS IVO , BAUER MATTHIAS
IPC分类号： C30B25/02 , C30B29/08 , C30B29/52 , H01L21/20 , H01L21/205 , H01L21/31 , C23C16/00 , C30B23/00 , H01L31/072
CPC分类号： C30B29/08 , C30B25/02 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02661
摘要： Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing (305) to lower deposition temperatures (315) for Ge-containing layers, Si or Ge compounds are provided (310) to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers (110) result. Retrograded relaxed SiGe (115) is also provided between a relaxed, high Ge-content seed layer (110) and an overlying strained layer (120).
摘要翻译：用于沉积诸如外延Ge和SiGe膜的外延膜的方法。在对于含锗层从高温处理（305）到较低沉积温度（315）的冷却期间，向基板提供（310）Si或Ge化合物。产生平滑，薄，相对缺陷的Ge或SiGe层（110）。在弛豫的高Ge含量种子层（110）和上覆应变层（120）之间还提供了退化的松弛SiGe（115）。

9. 发明申请

WO0166832A3 GRADED THIN FILMS 审中-公开
标题翻译：分级薄膜
公开(公告)号：WO0166832A3
公开(公告)日：2002-02-14
申请号：PCT/US0106746
申请日：2001-03-02
申请人： ASM INC
发明人： WERKHOVEN CHRISTIAAN J , RAAIJMAKERS IVO , HAUKKA SUVI P
IPC分类号： C23C16/30 , C23C16/02 , C23C16/34 , C23C16/40 , C23C16/44 , C23C16/455 , C23C16/48 , C30B25/14 , H01L21/28 , H01L21/285 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L29/51 , H01L21/205
CPC分类号： H01L21/28185 , C23C16/029 , C23C16/34 , C23C16/401 , C23C16/403 , C23C16/405 , C23C16/452 , C23C16/45529 , C23C16/45531 , C23C16/45534 , C30B25/14 , H01L21/0214 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28194 , H01L21/28202 , H01L21/28562 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/3185 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2221/1089 , H01L2924/0002 , Y10T428/24942 , Y10T428/2495 , H01L2924/00
摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles (301) or (450, 455, 460, 470) including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources (306 or 460) are introduced during the cyclical process. A graded gate dielectric (72) is thereby provided, even for extremely thin layers. The gate dielectric (72) as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric (72) can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (432) (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses (460) can gradually increase in frequency, forming a graded transition region (434), until pure copper (436) is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.
摘要翻译：通过原子层沉积形成薄膜，由此在包括自限制化学的交替脉冲的循环（301）或（450,455,460,470）期间，膜的组成可以从单层变化到单层。在所示实施例中，在循环过程中引入了不同量的杂质源（306或460）。因此，即使对于非常薄的层，也提供了渐变栅极电介质（72）。薄的2nm的栅极电介质（72）可以从纯氧化硅到氧氮化物变化为氮化硅。类似地，栅极电介质（72）可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。在另一个实施例中，金属氮化物（432）（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。在交替沉积过程中，铜可以被引入，例如在单独的脉冲中，并且铜源脉冲（460）可以逐渐增加频率，形成渐变过渡区（434），直到形成纯铜（436）上表面。有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。

10. 发明申请

WO0016380A9 METHOD AND APPARATUS FOR COOLING SUBSTRATES 审中-公开
标题翻译：用于冷却基板的方法和设备
公开(公告)号：WO0016380A9
公开(公告)日：2000-12-07
申请号：PCT/US9919687
申请日：1999-08-26
申请人： ASM INC , RAAIJMAKERS IVO
发明人： RAAIJMAKERS IVO
IPC分类号： C23C16/44 , C23C16/54 , C23C16/56 , C30B25/10 , H01L21/00 , H01L21/205 , C30B31/12
CPC分类号： H01L21/67109 , C23C16/54 , C23C16/56 , C30B25/10
摘要： Methods and apparatuses are provided for cooling semiconductor substrates prior to handling. In one embodiment, a substrate and support structure combination is lifted after high temperature processing to a cold wall of a thermal processing chamber, which acts as a heat sink. Conductive heat transfer across a small gap from the substrate to the heat sink speeds wafer cooling prior to handling the wafer (e.g., with a robot). In another embodiment, a separate plate is kept cool within a pocket during processing, and is moved close to the substrate and support after processing. In yet another embodiment, a cooling station between a processing chamber and a storage cassette includes two movable cold plates, which are movable to positions closely spaced on either side of the wafer.
摘要翻译：提供用于在处理之前冷却半导体衬底的方法和设备。在一个实施例中，在高温处理之后将衬底和支撑结构组合提升到充当散热器的热处理室的冷壁。从基板到散热器的小间隙中的导热传递在处理晶片之前（例如用机器人）加速晶片冷却。在另一个实施例中，分离的板在处理期间保持在袋内冷却，并且在处理之后移动靠近基底和支撑件。在又一个实施例中，处理室和储存盒之间的冷却站包括两个可移动的冷却板，其可移动到在晶片的任一侧上紧密间隔的位置。

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