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1. 发明申请

WO2005055434A1 APPARATUS AND METHOD FOR CALCULATING PATH METRIC DIFFERENCES IN A MAXIMUM LIKELIHOOD DETECTOR OR DECODER 审中-公开
标题翻译：用于计算最大似然检测器或解码器中的路径差异的装置和方法
公开(公告)号：WO2005055434A1
公开(公告)日：2005-06-16
申请号：PCT/GB2004/002537
申请日：2004-06-11
申请人： ARITHMATICA LIMITED , ATKINSON, Nicholas , JACKSON, Robert, Charles , ZABORONSKI, Oleg, Vitalievich , DRANE, Theo , VITYAEV, Andrei
发明人： ATKINSON, Nicholas , JACKSON, Robert, Charles , ZABORONSKI, Oleg, Vitalievich , DRANE, Theo , VITYAEV, Andrei
IPC分类号： H03M13/41
CPC分类号： H03M13/395 , H03M13/4107 , H03M13/4138
摘要： A calculating apparatus for use in a maximum likelihood detector, the calculating apparatus comprising: receiving means for receiving convolution encoded data which may include added noise; first calculating means for calculating a first component of a first path metric difference between two possible sequences of states corresponding to said convolution encoded data, the two sequences each having a length equal to a constraint length of the convolution encoded data, and the two sequences starting at a same state and ending at a same state, adapted to calculate said first component using said convolution-encoded data and using convolution encoding parameters of said convolution-encoded data, wherein the first component is independent of the two sequences; and second calculating means for calculating a second component of said first path metric difference using said two sequences, wherein the second component is independent of said convolution encoded data; and adding or substracting the first and second components to obtain said first path metric difference. Hence, the amount of processing in high-speed implementations of radix-2 n Viterbi detectors or decoders is reduced.
摘要翻译：一种在最大似然检测器中使用的计算装置，所述计算装置包括：接收装置，用于接收可包括附加噪声的卷积编码数据; 第一计算装置，用于计算与所述卷积编码数据相对应的两个可能状态序列之间的第一路径量度差的第一分量，每个具有等于卷积编码数据的约束长度的长度的两个序列，以及两个序列开始在相同状态下并以相同状态结束，适于使用所述卷积编码数据计算所述第一分量，并使用所述卷积编码数据的卷积编码参数，其中所述第一分量独立于所述两个序列; 以及第二计算装置，用于使用所述两个序列来计算所述第一路径量度差的第二分量，其中所述第二分量与所述卷积编码数据无关; 以及添加或减少第一和第二分量以获得所述第一路径度量差。因此，降低了基数-2维特比检测器或解码器的高速实现中的处理量。

2. 发明申请

WO2004112258A1 HIGH SPEED VITERBI DECODING AND DETECTION USING AN ITERATIVE TRELLIS COLLAPSING ALGORITHM 审中-公开
标题翻译：高速VITERBI解码和检测使用迭代TRELLIS收缩算法
公开(公告)号：WO2004112258A1
公开(公告)日：2004-12-23
申请号：PCT/GB2004/002536
申请日：2004-06-11
申请人： ARITHMATICA LIMITED , ZABORONSKI, Oleg, Vitalievich , VITYAEV, Andrei
发明人： ZABORONSKI, Oleg, Vitalievich , VITYAEV, Andrei
IPC分类号： H03M13/41
CPC分类号： H03M13/6572 , H03M13/395 , H03M13/3966 , H03M13/3972 , H03M13/41 , H03M13/4107
摘要： A maximum likelihood detector or decoder for receiving a stream of data values which correspond to ideal values but which may include added noise, and outputting information specifying a sequence of states of maximum likelihood selected from a plurality of possible states corresponding to the stream of data values, said ideal values being determined by the possible states, the maximum likelihood detector comprising: a transition metric preprocessor programmed to obtain or calculate first weighting values indicating likelihoods that each data value corresponds respectively to each of a plurality of said ideal data values; a plurality of processors arranged in a hierarchical structure, wherein each processor in a lowest level of the hierarchy is programmed to use a plurality of the first weighting values to calculate second weighting values representing section transition metrics and indicating respective likelihoods that a section of the stream of data values corresponds to each of a plurality of possible state sequences, the section comprising one or more possible initial state and one or more possible final states.
摘要翻译：一种最大似然检测器或解码器，用于接收对应于理想值但可包含附加噪声的数据值流，并且输出指定从与数据值对应的多个可能状态中选择的最大似然状态序列的信息所述理想值由可能的状态确定，所述最大似然检测器包括：编程为获得或计算指示每个数据值分别对应于多个所述理想数据值中的每一个的可能性的第一加权值的转移度量预处理器; 以层次结构排列的多个处理器，其中该层级的最低级别中的每个处理器被编程为使用多个第一加权值来计算表示部分转换度量的第二加权值，并指示相应的可能性，即流的一部分数据值对应于多个可能状态序列中的每一个，该部分包括一个或多个可能的初始状态和一个或多个可能的最终状态。

3. 发明申请

WO2010039874A1 METHOD AND APPARATUS FOR SOFT DATA GENERATION FOR MEMORY DEVICES USING DECODER PERFORMANCE FEEDBACK 审中-公开
标题翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置
公开(公告)号：WO2010039874A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/059087
申请日：2009-09-30
申请人： LSI CORPORTION , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , WILLIAMSON, Clifton , YEN, Johnson
发明人： HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , WILLIAMSON, Clifton , YEN, Johnson
IPC分类号： G11C16/34 , G11C16/26 , G11C7/10 , G11C11/56
CPC分类号： G11C16/26 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/1032 , G06F2212/2022 , G11C7/02 , G11C7/04 , G11C11/16 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5634
摘要： Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.
摘要翻译：用于使用解码器性能反馈的存储器件的软数据生成的方法和装置。通过从解码器获得性能反馈，在存储器件中产生至少一个软数据值; 基于性能反馈获得误差统计; 以及基于所获得的误差统计量生成所述至少一个软数据值。性能反馈包括解码比特中的一个或多个，基于由解码器解码的数据的多个错误比特和多个不满足的奇偶校验。

4. 发明申请

WO2010002942A1 METHOD AND APPARATUS FOR WRITE-SIDE INTERCELL INTERFERENCE MITIGATION IN FLASH MEMORIES 审中-公开
标题翻译：用于闪存中写入边缘干扰减轻的方法和装置
公开(公告)号：WO2010002942A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/049327
申请日：2009-06-30
申请人： LSI CORPORATION , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
发明人： HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for write-side intercell interference mitigation in flash memories. A flash memory device is written by obtaining program data to be written to at least one target cell in the flash memory; obtaining one or more bits of program data for at least one aggressor cell to be programmed later than the target cell: and precompensating for intercell interference for the target cell by generating precompensated program values. The aggressor cells comprise one or more cells adjacent to the target cell, such as adjacent cells in a same wordline as the target cell and/or cells in an upper or lower adjacent wordline to the target cell. The precompensated program values for the target cell are optionally provided to the flash memory.
摘要翻译：提供了用于闪存中的写侧小区间干扰减轻的方法和装置。通过获得写入到闪速存储器中的至少一个目标单元的程序数据来写入闪速存储器件; 为至少一个侵略者单元获得待编程的比目标小区晚的一个或多个程序数据位;并且通过产生预补偿的程序值来预补偿目标小区的小区间干扰。侵略者细胞包括与靶细胞相邻的一个或多个细胞，例如与靶细胞相同的字线中的相邻细胞和/或与靶细胞的上或下相邻字线中的细胞。目标单元的预补偿程序值可选地提供给闪存。

5. 发明申请

WO2010002941A1 METHODS AND APPARATUS FOR READ-SIDE INTERCELL INTERFERENCE MITIGATION IN FLASH MEMORIES 审中-公开
标题翻译：闪存中读取边界干扰减轻的方法和装置
公开(公告)号：WO2010002941A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/049326
申请日：2009-06-30
申请人： LSI CORPORATION , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
发明人： HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for read-side intercell interference mitigation in flash memories, A flash memory device is read by obtaining a read value for at least one target cell; obtaining a value representing a voltage stored in at least one aggressor cell that was programmed after the target cell; determining intercell interference for the target cell from the at least one aggressor cell; and obtaining a new read value that compensates for the intercell interference by removing the determined intercell interference from the read value for the at least one target cell. The new read value can optionally be provided to a decoder. In an iterative implementation, one or more intercell interference mitigation parameters can be adjusted if a decoding error occurs.
摘要翻译：提供了用于闪速存储器中的读侧细胞间干扰减轻的方法和装置。通过获得至少一个目标单元的读取值来读取闪速存储器件; 获得代表在目标小区之后编程的至少一个攻击者小区中存储的电压的值; 从所述至少一个侵略者小区确定所述目标小区的小区间干扰; 以及通过从所述至少一个目标小区的读取值中去除所确定的小区间干扰来获得补偿小区间干扰的新的读取值。可以可选地将新的读取值提供给解码器。在迭代实现中，如果发生解码错误，则可以调整一个或多个小区间干扰减轻参数。

6. 发明申请

WO2010039866A1 METHODS AND APPARATUS FOR SOFT DATA GENERATION FOR MEMORY DEVICES 审中-公开
标题翻译：用于存储器件的软数据生成的方法和装置
公开(公告)号：WO2010039866A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/059077
申请日：2009-09-30
申请人： LSI CORPORATION , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , WILLIAMSON, Clifton , YEN, Johnson
发明人： HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , WILLIAMSON, Clifton , YEN, Johnson
IPC分类号： G11C16/26 , G11C16/34 , G11C7/10 , G11C11/56
CPC分类号： G11C16/26 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/1032 , G06F2212/2022 , G11C7/02 , G11C7/04 , G11C11/16 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5634
摘要： Methods and apparatus are provided for soft data generation for memory devices. At least one soft data value is generated for a memory device, by obtaining at least one hard read value; and generating the soft data value associated with the at least one hard read value based on statistics for reading the hard read value. The hard read value may be one or more of data bits, voltage levels, current levels and resistance levels. The generated soft data value may be one or more of (i) a soft read value that is used to generate one or more log likelihood ratios, and (ii) one or more log likelihood ratios. The statistics comprise one or more of bit-based statistics and cell-based statistics. The statistics may also optionally comprise pattern-dependent disturbance of at least one aggressor cell on the target cell, as well as location-specific statistics. At least one soft data value can be generated for a memory device, by obtaining a soft read value; and generating the soft data value associated with the soft read value based on statistics for reading the soft read value, wherein the statistics comprise one or more of location-specific statistics and pattern-dependent statistics.
摘要翻译：为存储器件的软数据生成提供了方法和装置。通过获得至少一个硬读取值，为存储器件生成至少一个软数据值; 以及基于用于读取硬读取值的统计量来生成与所述至少一个硬读取值相关联的软数据值。硬读取值可以是数据位，电压电平，电流电平和电阻电平中的一个或多个。所产生的软数据值可以是（i）用于产生一个或多个对数似然比的软读取值的一个或多个，以及（ii）一个或多个对数似然比。统计信息包括基于位的统计信息和基于单元的统计信息中的一个或多个。统计还可以任选地包括目标小区上的至少一个攻击者小区的模式相关干扰，以及位置特定统计。可以通过获得软读取值来为存储器件生成至少一个软数据值; 以及基于用于读取所述软读取值的统计信息来生成与所述软读取值相关联的软数据值，其中所述统计信息包括位置特定统计信息和模式相关统计信息中的一个或多个。

7. 发明申请

WO2010011692A1 METHODS AND APPARATUS FOR PROGRAMMING MULTIPLE PROGRAM VALUES PER SIGNAL LEVEL IN FLASH MEMORIES 审中-公开
标题翻译：用于编程闪存中每个信号电平的多个程序值的方法和装置
公开(公告)号：WO2010011692A1
公开(公告)日：2010-01-28
申请号：PCT/US2009/051314
申请日：2009-07-21
申请人： LSI CORPORATION , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
发明人： HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： Methods and apparatus are provided for programming multiple program values per signal level in flash memories. A flash memory device having a plurality of program values is programmed by programming the flash memory device for a given signal level, wherein the programming step comprises a programming phase and a plurality of verify phases. In another variation, a flash memory device having a plurality of program values is programmed, and the programming step comprises a programming phase and a plurality of verify phases, wherein at least one signal level comprises a plurality of the program values. The signal levels or the program values (or both) can be represented using one or more of a voltage, a current and a resistance.
摘要翻译：提供了用于在闪速存储器中编程每个信号电平的多个程序值的方法和装置。具有多个编程值的闪速存储器件通过针对给定的信号电平对闪速存储器件进行编程来编程，其中编程步骤包括编程阶段和多个验证阶段。在另一个实施例中，编程具有多个编程值的闪速存储器件，并且编程步骤包括编程阶段和多个验证阶段，其中至少一个信号电平包括多个程序值。可以使用电压，电流和电阻中的一个或多个来表示信号电平或程序值（或两者）。

8. 发明申请

WO2010002945A1 METHODS AND APPARATUS FOR INTERCELL INTERFERENCE MITIGATION USING MODULATION CODING 审中-公开
标题翻译：使用调制编码的INTERCELL干扰减轻的方法和装置
公开(公告)号：WO2010002945A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/049330
申请日：2009-06-30
申请人： LSI Corporation , GRAEF, Nils , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , VITYAEV, Andrei , YEN, Johnson
发明人： GRAEF, Nils , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , VITYAEV, Andrei , YEN, Johnson
IPC分类号： G11C16/10 , G11C11/56 , G11C7/10 , H03M13/00
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.
摘要翻译：提供了使用调制编码的小区间干扰减轻的方法和装置。在闪速存储器的编程期间，执行调制编码，其选择用于编程闪速存储器的一个或多个级别，使得闪存中的减少数量的单元被编程为具有违反一个或多个预定标准的值。在读取闪速存储器期间，执行调制解码，其将一个或多个级别分配给闪速存储器中的单元，使得闪存中的小数量的单元以违反一个或多个预定准则的值被读取。预定义的标准可以例如基于由编程的小区引起的干扰量的一个或多个; 编程单元的电压移位：由编程单元存储的电压; 通过编程单元的电流变化量; 以及通过编程单元的电流量。

9. 发明申请

WO2010039869A1 METHODS AND APPARATUS FOR SOFT DATA GENERATION FOR MEMORY DEVICES USING REFERENCE CELLS 审中-公开
标题翻译：用于使用参考电池的存储器件的软数据生成的方法和装置
公开(公告)号：WO2010039869A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/059081
申请日：2009-09-30
申请人： LSI CORPORATION , BURGER, Harley, F., Jr. , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
发明人： BURGER, Harley, F., Jr. , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
IPC分类号： G11C16/26 , G11C16/34 , G11C7/10 , G11C11/56
CPC分类号： G11C16/26 , G06F11/1012 , G06F11/1068 , G06F12/0246 , G06F2212/1032 , G06F2212/2022 , G11C7/02 , G11C7/04 , G11C11/16 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5634
摘要： Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values.
摘要翻译：提供了用于使用参考单元的存储器件的软数据生成的方法和装置。通过将已知数据写入一个或多个参考单元，在存储器件中产生至少一个软数据值; 读取一个或多个参考细胞; 基于读取的一个或多个参考单元获得读取统计量; 以及基于获得的读取统计量获得所述至少一个软数据值。可以可选地为存储器阵列的一个或多个所需位置获得读取统计; 或者对于一个或多个侵略者细胞中的给定模式PATT。读取统计可以可选地包括为多个可能值获得的不对称统计量。

10. 发明申请

WO2010002948A1 METHODS AND APPARATUS FOR SOFT DEMAPPING AND INTERCELL INTERFERENCE MITIGATION IN FLASH MEMORIES 审中-公开
标题翻译：闪存记忆体中软扫描和干扰抑制的方法与装置
公开(公告)号：WO2010002948A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/049333
申请日：2009-06-30
申请人： LSI CORPORATION , HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
发明人： HARATSCH, Erich, F. , IVKOVIC, Milos , KRACHKOVSKY, Victor , MILADINOVIC, Nenad , VITYAEV, Andrei , YEN, Johnson
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G11C16/3427 , G06F11/1072 , G11C5/00 , G11C7/02 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step.
摘要翻译：提供了用于闪存中的软解映射和小区间干扰减轻的方法和装置。在一个实施例中，通过为闪速存储器中的至少一个目标单元获得测量的读取值r来读取能够存储每个单元的至少两个数据电平s的闪速存储器件中的目标单元; 获得表示对闪速存储器中的至少一个侵略者单元存储的数据的值h; 基于存储在所述闪速存储器的至少一部分中的值的模式来选择一个或多个概率密度函数，其中所述概率密度函数包括所述闪存中的所述至少一个目标小区上的一个或多个攻击者小区的模式相关干扰记忆; 基于测量的读取值r来评估至少一个所选择的概率密度函数; 以及基于所述评估步骤的结果计算一个或多个对数似然比。

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