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    • 6. 发明申请
    • ULTRA WIDEBAND TRANSCEIVER ARCHITECTURE AND METHOD
    • 超宽带收发器体系结构和方法
    • WO2009057123A2
    • 2009-05-07
    • PCT/IL2008/001692
    • 2008-12-30
    • A.M.P.S. ADVANCED MICROPOWER SEMICONDUCTORS L.T.D.PRIMO, HaimHOLZER, ReuvenIVRY, Ygal
    • PRIMO, HaimHOLZER, ReuvenIVRY, Ygal
    • H04J14/02
    • H04L27/2647H04L27/2684
    • In the technology known today, UWB transceiver power consumption is not efficient and too high. We have solved this problem. In our patent we have presented our innovationist UWB transceiver circuit, which could be used for preamble based OFDM or pilot based OFDM reception. In IEEE P802.15-03/268r3 it is reported that UWB OFDM receiver power consumption at 480Mbits/sec, when implemented using traditional digital method, is 323mwatts for 130nm, and 236mwatts for 90nm. We have found that implementation of the same receiver using our new innovationist OFDM receiver, working at 480Mhz, consumes about 40mwatts. It is clear, in terms of power consumptions, that our OFDM receiver implementation is 8 times lower than the lowest power consumption known today by OFDM receiver circuit.
    • 在当今已知的技术中,UWB收发器功耗不高并且太高。 我们已经解决了这个问题。 在我们的专利中,我们展示了我们的创新型UWB收发器电路,该电路可用于基于前导码的OFDM或基于导频的OFDM接收。 在IEEE P802.15-03 / 268r3中,据报道,使用传统数字方法实现的480Mbits / sec的UWB OFDM接收器功耗在130nm下为323mW,在90nm下为236mW。 我们发现,使用我们新的创新型OFDM接收器,在480Mhz下工作,实现相同的接收器,功耗约为40mW。 就功耗而言,很显然,我们的OFDM接收器实现比OFDM接收器电路目前已知的最低功耗低8倍。
    • 7. 发明申请
    • NOVEL ULTRA LOW POWER OFDM RECEIVER COMPONENTS
    • 新型超低功耗OFDM接收器组件
    • WO2009122405A2
    • 2009-10-08
    • PCT/IL2009/000352
    • 2009-04-05
    • A.M.P.S. ADVANCED MICROPOWER SEMICONDUCTORS L.T.D.PRIMO, HaimHOLZER, ReuvenIVRY, Ygal
    • PRIMO, HaimHOLZER, ReuvenIVRY, Ygal
    • H04J14/04
    • H04L27/2647
    • The theme of our patent is an ultra low power components for Orthogonal Frequency Division Multiplexing (OFDM) based receiver. A new and innovationist OFDM receiver components ("our OFDM receiver components"), based on discrete time analog signal processing, are described in this patent application. OFDM receiver circuit is usually related to a communication field, where it is used to receive and decode a transmitted data. OFDM receiver circuit gets at its input OFDM modulated signals, and performs all necessary tasks, in order to decode the received data. OFDM signal comprised of multiple orthogonal carrier (103a- 105a), in which each one carries different data symbol. The summation of all carrier symbols comprises the data. To perform the receiving operation, an OFDM receiver must first perform detection, synchronization, parameter and channel estimation, then, a Fast Fourier Transform (FFT) is applied, and then, equalization is performed, and the last stage, is the de-interleaving and the error correction. All tasks above require complicated computational operations, such as additions, multiplications. Therefore, if implemented in a digital way, as it is with the current known technology, a significant high power is consumed by the receiver. Our OFDM receiver components are built and designed to work with discrete time analog signals, based on extremely low power additions, multiplications operations, and therefore achieves significant power reduction, compared to its digital counter implementation.
    • 我们的专利主题是基于正交频分复用(OFDM)接收机的超低功耗组件。 在本专利申请中描述了基于离散时间模拟信号处理的新的和创新的OFDM接收器组件(“我们的OFDM接收器组件”)。 OFDM接收机电路通常与通信领域相关,其中它用于接收和解码发送的数据。 OFDM接收机电路获取其输入的OFDM调制信号,并执行所有必要的任务,以解码接收到的数据。 OFDM信号由多个正交载波(103a-105a)组成,其中每个载波携带不同的数据符号。 所有载波符号的总和包括数据。 为了执行接收操作,OFDM接收机必须首先执行检测,同步,参数和信道估计,然后应用快速傅里叶变换(FFT),然后进行均衡,最后一个阶段是解交织 和纠错。 上述所有任务都需要复杂的计算操作,如添加,乘法运算。 因此,如果以数字方式实现,与目前已知的技术一样,接收机消耗了显着的高功率。 与其数字计数器实现相比,我们的OFDM接收器组件被构建和设计为基于极低功率添加,乘法运算来处理离散时间模拟信号,因此实现了显着的功率降低。
    • 10. 发明申请
    • GALOIS FIELD MULTIPLY/MULTIPLY-ADD MULTIPLY ACCUMULATE
    • GALOIS场多项式/多项式加法积分
    • WO2003048921A1
    • 2003-06-12
    • PCT/US2002/038501
    • 2002-12-02
    • ANALOG DEVICES, INC.
    • STEIN, YosefPRIMO, HaimSAPIR, Yaniv
    • G06F7/00
    • G06F7/724
    • A Galois field multiply/multiply-add/multiply-accumulate system (10) includes a multiplier circuit for multiplying two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit responsive to the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; storage circuit for supplying to the Galois field linear transformer circuit a set of coefficient for predicting the modulo remainder for a predetermined irreducible polynomial; and a Galois field adder circuit for adding the product of the multiplier circuit with a third polynomial with coefficients over a Galois field for performing the multiplication and add operations in a single cycle.
    • 伽罗瓦域乘法/乘法/乘法 - 累加系统(10)包括乘法器电路,用于将两个多项式与伽罗瓦域上的系数相乘以获得其乘积; 响应于乘法器电路的用于预测用于不可约多项式的多项式积的模余数的伽罗瓦域线性变换器电路; 存储电路,用于向伽罗瓦斯线性变压器电路提供用于预测预定不可约多项式的模余数的一组系数; 以及伽罗瓦域加法器电路,用于将乘法器电路的乘积与Galois域上的系数相加,以便在单个周期内执行乘法和相加操作。