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1. 发明申请

WO2006081049A2 IMPROVING BRANCH PREDICTION ACCURACY IN A PROCESSOR THAT SUPPORTS SPECULATIVE EXECUTION 审中-公开
标题翻译：在支持实施执行的处理器中提高分支预测精度
公开(公告)号：WO2006081049A2
公开(公告)日：2006-08-03
申请号：PCT/US2006000354
申请日：2006-01-05
申请人： SUN MICROSYSTEMS INC , CAPRIOLI PAUL , YIP SHERMAN H , CHAUDHRY SHAILENDER
发明人： CAPRIOLI PAUL , YIP SHERMAN H , CHAUDHRY SHAILENDER
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3844
摘要： One embodiment of the present invention provides a system which improves branch prediction accuracy in a processor that supports speculative-execution. During normal-execution mode, the system issues instructions in program order. Upon encountering a launch condition which causes a processor to enter a speculative-execution mode, the system performs a checkpoint and begins executing instructions in a speculative-execution mode. Upon encountering a branch instruction during speculative-execution mode, the system selects the subsequent instruction to be executed based on a current state of a branch predictor and does not update the current state of the branch predictor, thereby preventing the branch predictor from being incorrectly updated twice when re-executing the branch instruction after returning to normal-execution mode.
摘要翻译：本发明的一个实施例提供一种提高支持推测执行的处理器中的分支预测精度的系统。在正常执行模式下，系统以程序顺序发出指令。当遇到导致处理器进入推测执行模式的启动条件时，系统执行检查点并以推测执行模式开始执行指令。在推测执行模式期间遇到分支指令时，系统基于分支预测器的当前状态选择要执行的后续指令，并且不更新分支预测器的当前状态，从而防止分支预测器被错误地更新在返回到正常执行模式后重新执行分支指令时，两次。

2. 发明申请

WO2005121949A3 AVOIDING REGISTER READ-AFTER-WRITE HAZARDS AFTER SPECULATIVE EXECUTION 审中-公开
公开(公告)号：WO2005121949A3
公开(公告)日：2005-12-22
申请号：PCT/US2005/006185
申请日：2005-02-25
申请人： SUN MICROSYSTEMS, INC. , CHAUDHRY, Shaildender , CAPRIOLI, Paul , YIP, Sherman, H.
发明人： CHAUDHRY, Shaildender , CAPRIOLI, Paul , YIP, Sherman, H.
IPC分类号： G06F9/38
摘要： One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During operation, the system issues instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commences execution in the speculative-execution mode. Upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the system uses the checkpoint to resume execution in the normal-execution mode from the launch-point instruction. In doing so, the system ensures that entries. that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for in order to prevent register RAW hazard when resuming execution from the launch-point instruction.

3. 发明申请

WO2005121949A2 AVOIDING REGISTER RAW HAZARDS WHEN RETURNING FROM SPECULATIVE EXECUTION 审中-公开
标题翻译：当从行政执行返回时避免注册原始危险
公开(公告)号：WO2005121949A2
公开(公告)日：2005-12-22
申请号：PCT/US2005006185
申请日：2005-02-25
申请人： SUN MICROSYSTEMS INC , CHAUDHRY SHAILDENDER , CAPRIOLI PAUL , YIP SHERMAN H
发明人： CHAUDHRY SHAILDENDER , CAPRIOLI PAUL , YIP SHERMAN H
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During operation, the system issues instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commences execution in the speculative-execution mode. Upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the system uses the checkpoint to resume execution in the normal-execution mode from the launch-point instruction. In doing so, the system ensures that entries. that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for in order to prevent register RAW hazard when resuming execution from the launch-point instruction.
摘要翻译：本发明的一个实施例提供一种从推测执行模式返回时避免寄存器读写（RAW）危险的系统。该系统在具有按顺序架构的处理器内工作，其中处理器包括短延迟记分板，其延迟取决于未完成的短延迟指令的指令的发布。在操作期间，系统在以正常执行模式执行程序期间以程序顺序发出执行指令。在导致处理器进入推测执行模式的指令（发起点指令）期间遇到条件（启动条件）时，系统生成检查点，该检查点随后可用于将程序的执行返回到启动点指令，并以推测执行模式开始执行。当遇到导致处理器离开推测执行模式并返回到启动点指令的条件时，系统使用检查点在正常执行模式下从启动点指令恢复执行。在这样做时，系统确保输入。在进入推测执行模式之前处于短暂延迟记分板中，并且尚未解决的情况被考虑，以便在从启动点指令恢复执行时防止寄存器RAW危险。

4. 发明申请

WO2006081049A3 IMPROVING BRANCH PREDICTION ACCURACY IN A PROCESSOR THAT SUPPORTS SPECULATIVE EXECUTION 审中-公开
公开(公告)号：WO2006081049A3
公开(公告)日：2006-08-03
申请号：PCT/US2006/000354
申请日：2006-01-05
申请人： SUN MICROSYSTEMS, INC. , CAPRIOLI, Paul , YIP, Sherman, H. , CHAUDHRY, Shailender
发明人： CAPRIOLI, Paul , YIP, Sherman, H. , CHAUDHRY, Shailender
IPC分类号： G06F9/38
摘要： One embodiment of the present invention provides a system which improves branch prediction accuracy in a processor that supports speculative-execution. During normal-execution mode, the system issues instructions in program order. Upon encountering a launch condition which causes a processor to enter a speculative-execution mode, the system performs a checkpoint and begins executing instructions in a speculative-execution mode. Upon encountering a branch instruction during speculative-execution mode, the system selects the subsequent instruction to be executed based on a current state of a branch predictor and does not update the current state of the branch predictor, thereby preventing the branch predictor from being incorrectly updated twice when re-executing the branch instruction after returning to normal-execution mode.

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