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    • 6. 发明申请
    • DIGITAL DEMODULATOR
    • 数字解调器
    • WO1994021073A1
    • 1994-09-15
    • PCT/JP1994000370
    • 1994-03-09
    • TOYO COMMUNICATION EQUIPMENT CO., LTD.WADA, Yoshio
    • TOYO COMMUNICATION EQUIPMENT CO., LTD.
    • H04L27/22
    • H04L7/0054H04L27/2332H04L2027/0032H04L2027/0055H04L2027/0057
    • A clock reproducing circuit which can generate a good demodulation signal by detecting the timing point of the demodulation in an extremely short period of time; a digital demodulator which uses this clock reproducing circuit; a device for estimating a bit error rate of which deterioration of communication efficiency is limited to the extremity; and an AFC circuit which is capable of correcting a frequency drift in the correct direction exactly even when the frequency drift is great. The digital demodulator demodulates a signal detected by detecting a modulated wave by a given detector in accordance with timing clock signals. The demodulator comprises means for detecting the correlation of every two extraction points adjacent to each other by sampling a signal in the process of demodulation at a plurality of extraction points predetermined for every unit data cycle (symbol cycle); means for comparing the sizes of the correlations detected by the correlation detecting means, determining two pairs of extraction points of the greatest and second greatest sizes of correlation, and generating timing clock signals in accordance with the determination; and means for shifting the phase of signal in the process of demodulation in order to equalize the correlation sizes detected by the two pairs of the extraction points. The device for estimating a bit error rate detects the correlation of every two extracted points adjacent to each other by sampling a signal in the process of demodulation at a plurality of extraction points predetermined for every unit data cycle (symbol cycle), and estimates the bit error rate in accordance with the distribution of the detected correlations. Furthermore, in the AFC circuit, the frequency drift of the modulated wave is corrected by comparing the bit error rate estimated by the said bit error estimating device and the measured bit error rate.
    • 时钟再现电路,其可以通过在极短时间内检测解调的定时点来产生良好的解调信号; 使用该时钟再现电路的数字解调器; 用于估计通信效率的恶化被限制到末端的误码率的装置; 以及即使当频率漂移大时也能够正确校正频率漂移的AFC电路。 数字解调器通过根据定时时钟信号通过给定检测器检测调制波来解调检测到的信号。 解调器包括用于通过在针对每个单位数据周期(符号周期)预定的多个提取点处对解调过程中的信号进行采样来检测彼此相邻的每两个提取点的相关性的装置; 用于比较由相关检测装置检测的相关尺寸的大小的装置,确定具有最大和最大相关尺寸的两对提取点,并根据该确定产生定时时钟信号; 以及用于在解调过程中移位信号的相位的装置,以便均衡由两对提取点检测的相关尺寸。 用于估计误码率的装置通过对在每个单位数据周期(符号周期)预定的多个提取点处的解调处理中的信号进行采样来检测彼此相邻的每两个提取点的相关性,并且估计该位 错误率根据检测到的相关性的分布。 此外,在AFC电路中,通过比较由所述比特误差估计装置估计的比特误码率和测量的比特误码率来校正调制波的频率漂移。