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1. 发明申请

WO2011107161A1 RESISTANCE COMPONENT 审中-公开
标题翻译：电阻元件
公开(公告)号：WO2011107161A1
公开(公告)日：2011-09-09
申请号：PCT/EP2010/052857
申请日：2010-03-05
申请人： EPCOS AG , VAN DEN OEVER, Léon C. M. , BALM, Bart , BOUWMAN, Jeroen
发明人： VAN DEN OEVER, Léon C. M. , BALM, Bart , BOUWMAN, Jeroen
IPC分类号： H01L27/085 , G05F1/56
CPC分类号： H01L27/085 , H01L27/0802
摘要： A resistance component comprises a multitude of pHEMTs (10, 20, 30, 40, 50, 60, 70, 80) which are connected in series.
摘要翻译：电阻分量包括串联连接的大量pHEMT（10,20,30,40,50,60,70,80）。

2. 发明申请

WO2011063829A1 LOW-CURRENT LOGIC PLUS DRIVER CIRCUIT 审中-公开
标题翻译：低电流逻辑加速电路
公开(公告)号：WO2011063829A1
公开(公告)日：2011-06-03
申请号：PCT/EP2009/065760
申请日：2009-11-24
申请人： EPCOS AG , VAN DEN OEVER, Léon C. M. , SPITS, Erwin
发明人： VAN DEN OEVER, Léon C. M. , SPITS, Erwin
IPC分类号： H03K19/094 , H03K19/0952
CPC分类号： H03K19/09421 , H03K19/09407 , H03K19/0952
摘要： The low-current circuit comprises a logic stage (E3, E4, E5), an inverter stage (E8), and a driver stage (E9, E10). The logic stage and the inverter stage are provided with current limiters, which comprise a D-mode feedback transistor (D1; D2) and a component that generates a voltage drop (E1, E2; E6, E7). A feedback loop (FL) connects the source and the gate of the D-mode feedback transistor via this component. The driver stage comprises E-mode transistors (E9, E10) connected in a totem pole that drive a D-mode transistor and an E-mode transistor to connect and disconnect the load circuit. This circuit provides high current capability in the on-state and has negligible current in the off-state.
摘要翻译：低电流电路包括逻辑级（E3，E4，E5），反相器级（E8）和驱动级（E9，E10）。逻辑级和反相器级配有电流限制器，其包括D型反馈晶体管（D1; D2）和产生电压降（E1，E2; E6，E7）的元件。反馈回路（FL）经由该部件连接D型反馈晶体管的源极和栅极。驱动器级包括连接在驱动D模式晶体管的图腾柱中的E型晶体管（E9，E10）和用于连接和断开负载电路的E型晶体管。该电路在导通状态下提供高电流能力，并且在关断状态下具有可忽略的电流。

3. 发明申请

WO2011107160A1 BANDGAP REFERENCE CIRCUIT AND METHOD FOR PRODUCING THE CIRCUIT 审中-公开
标题翻译：带状参考电路和制造电路的方法
公开(公告)号：WO2011107160A1
公开(公告)日：2011-09-09
申请号：PCT/EP2010/052856
申请日：2010-03-05
申请人： EPCOS AG , BOUWMAN, Jeroen , VAN DEN OEVER, Léon C. M.
发明人： BOUWMAN, Jeroen , VAN DEN OEVER, Léon C. M.
IPC分类号： G05F3/30
CPC分类号： G05F3/30
摘要： Bandgap reference circuit, comprising a voltage generator (VG) designed to produce a voltage or a current proportional to absolute temperature, a supply circuit (SC), designed to produce a supply for operating the voltage generator (VG), comprising a bias element (BS) and a control element (CS), and a bias circuit (BC), designed to produce a bias for operating the voltage generator (VG), comprising a bias element (BB) and a control element (CB). At least one of the control element (CS) of the supply circuit (SC) and the control element (CB) of the bias circuit (BC) comprises a pseudomorphic high-electron-mobility transistor or a hetero-junction bipolar transistor and/or at least one of the bias element (BS) of the supply circuit (SC) and the bias element (BB) of the bias circuit (BC) comprises a long-gate pseudomorphic high-electron-mobility transistor or a resistor. Method for producing the circuit wherein the pseudomorphic high-electron-mobility transistors and the hetero-junction bipolar transistors are produced using a GaAs BiFET technology process.
摘要翻译：带隙参考电路，包括设计成产生与绝对温度成正比的电压或电流的电压发生器（VG），设计用于产生用于操作电压发生器（VG）的电源的电源电路（SC），包括偏置元件 BS）和控制元件（CS）以及设计成产生用于操作电压发生器（VG）的偏压的偏置电路（BC），包括偏置元件（BB）和控制元件（CB）。供电电路（SC）的控制元件（CS）和偏置电路（BC）的控制元件（CB）中的至少一个包括伪形高电子迁移率晶体管或异质结双极晶体管和/或供电电路（SC）的偏置元件（BS）和偏置电路（BC）的偏置元件（BB）中的至少一个包括长栅极伪晶体高电子迁移率晶体管或电阻器。用于制造电路的方法，其中使用GaAs BiFET技术工艺制造假晶高电子迁移率晶体管和异质结双极晶体管。

4. 发明申请

WO2011107158A1 pHEMT HAVING A CHANNEL LENGTH LARGER THAN THE CHANNEL WIDTH 审中-公开
标题翻译：具有通道长度超过通道宽度的pHEMT
公开(公告)号：WO2011107158A1
公开(公告)日：2011-09-09
申请号：PCT/EP2010/052853
申请日：2010-03-05
申请人： EPCOS AG , VAN DEN OEVER, Léon C. M. , BALM, Bart , BOUWMAN, Jeroen
发明人： VAN DEN OEVER, Léon C. M. , BALM, Bart , BOUWMAN, Jeroen
IPC分类号： H01L21/335 , H01L29/10 , H01L29/778
CPC分类号： H01L29/1029 , H01L29/66462 , H01L29/778
摘要： A semiconductor device comprises a pHEMT which comprises a source (30), a drain (10) and a channel region (40) running between the source (30) and the drain (10), the channel region (40) being located at least partly beneath a gate electrode (20), the channel region (40) having a channel length and a channel width, the channel length being the total length of the channel region (40) which is located beneath the gate electrode (20), the channel width being a width of the channel region (40) beneath the gate electrode (20), wherein the channel length is equal or larger than the channel width.
摘要翻译：半导体器件包括pHEMT，其包括源（30），漏极（10）和在源极（30）和漏极（10）之间延伸的沟道区（40），沟道区（40）至少位于部分地在栅电极（20）下方，沟道区域（40）具有沟道长度和沟道宽度，沟道长度是位于栅电极（20）下方的沟道区域（40）的总长度，沟道宽度是栅电极（20）下方的沟道区域（40）的宽度，其中沟道长度等于或大于沟道宽度。

5. 发明申请

WO2011066862A1 BIPOLAR TRANSISTOR WITH LATERAL EMITTER AND COLLECTOR AND METHOD OF PRODUCTION 审中-公开
标题翻译：具有侧向发射器和收集器的双极晶体管及其生产方法
公开(公告)号：WO2011066862A1
公开(公告)日：2011-06-09
申请号：PCT/EP2009/066364
申请日：2009-12-03
申请人： EPCOS AG , VAN DEN OEVER, Léon C. M. , HUETING, Ray J. E.
发明人： VAN DEN OEVER, Léon C. M. , HUETING, Ray J. E.
IPC分类号： H01L29/423 , H01L29/778
CPC分类号： H01L29/42316 , H01L29/7787
摘要： The bipolar transistor comprises a substrate (1) of semiconductor material, a high-mobility layer (2) in the substrate,and a donor layer (3) adjacent to the high- mobility layer. An emitter terminal (4) forms an emitter contact (5) on the donor layer, and a collector terminal (6) forms a collector contact (7) on the donor layer. A base terminal (8) is electrically conductively connected with the high-mobility layer. The transistor can be produced in a HEMT technology or BiFET technology in GaAs.
摘要翻译：双极晶体管包括半导体材料的衬底（1），衬底中的高迁移率层（2）和与高迁移率层相邻的施主层（3）。发射极端子（4）在施主层上形成发射极触点（5），并且集电极端子（6）在施主层上形成集电极触点（7）。基极端子（8）与高迁移率层导电连接。晶体管可以采用HEMT技术或GaAs中的BiFET技术生产。

6. 发明申请

WO2011066863A1 SEMICONDUCTOR CHIP WITH BACKSIDE METALLIZATION AND ARRANGEMENT OF SAID CHIP ON A CARRIER 审中-公开
标题翻译：具有背面金属化的半导体芯片和载体上的固定芯片布置
公开(公告)号：WO2011066863A1
公开(公告)日：2011-06-09
申请号：PCT/EP2009/066367
申请日：2009-12-03
申请人： EPCOS AG , FRIC, Tomas , BOUWMAN, Jeroen , VAN DEN OEVER, Léon C. M.
发明人： FRIC, Tomas , BOUWMAN, Jeroen , VAN DEN OEVER, Léon C. M.
IPC分类号： H01L23/66 , H01L23/48
CPC分类号： H01L23/481 , H01L23/5227 , H01L23/645 , H01L23/66 , H01L24/48 , H01L2223/6627 , H01L2223/6644 , H01L2224/48091 , H01L2924/00014 , H01L2924/01055 , H01L2924/1423 , H01L2924/1903 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic device or circuit (4) at the front side (2) of a substrate (1) of semiconductor material with terminals (5) and a wiring electrically connected with the terminals is connected with a structured backside metallization (7) on the rear side. An interconnect (8) through the substrate is electrically connected with the backside metallization, and the interconnect and the backside metallization form part of the wiring. The chip (11) can be arranged on a carrier (10) comprising contact areas (15), which can be connected with the backside metallization or the terminals directly or via bond wires.
摘要翻译：在具有端子（5）的半导体材料的基板（1）的前侧（2）处的电子器件或电路（4）和与端子电连接的布线在后部与后面的结构化背面金属化（7）连接侧。通过衬底的互连（8）与背面金属化电连接，并且互连和背面金属化形成布线的一部分。芯片（11）可以布置在包括接触区域（15）的载体（10）上，该接触区域可以直接或通过接合线与后侧金属化或端子连接。

7. 发明申请

WO2011066861A1 POWER AMPLIFIER CIRCUIT AND FRONT END CIRCUIT 审中-公开
标题翻译：功率放大器电路和前端电路
公开(公告)号：WO2011066861A1
公开(公告)日：2011-06-09
申请号：PCT/EP2009/066355
申请日：2009-12-03
申请人： EPCOS AG , SPITS, Erwin , VAN DEN OEVER, Léon C. M.
发明人： SPITS, Erwin , VAN DEN OEVER, Léon C. M.
IPC分类号： H03F3/24 , H03F3/72 , H04B1/00 , H03F1/02 , H03F3/60 , H01P1/213 , H04B1/04
CPC分类号： H03F3/24 , H03F1/0277 , H03F3/602 , H03F3/72 , H03F2200/111 , H03F2200/429 , H03F2200/543 , H03F2203/7209 , H03F2203/7239 , H04B1/0483 , H04B2001/0408
摘要： A power amplifier circuit (DIPPA), comprising a driver stage (DR) which is applicable to provide a preamplified driver signal (S DR) dependent on a predetermined transmit signal. The power amplifier circuit (DIPPA) comprises also a frequency selector (DIP) which is electrically coupled to the driver stage (DR) and which is applicable to separate the driver signal (S DR) into a first and second signal (S 1,S_2). The first signal (S_l) is associated to a first predetermined and the second signal (S_2) is associated to a second predetermined frequency band. The power amplifier circuit (DIPPA) comprises at least a first and second power amplifier stage (PA1, PA2). The first and second power amplifier stage (PA1, PA2) are electrically coupled to the frequency selector (DIP). The first and second power amplifier stage (PA1, PA2) is operable to provide a first and second amplified signal (S_A1, S_2), respectively, dependent on the first and second signal (S_1, S_2), respectively.
摘要翻译：一种功率放大器电路（DIPPA），包括驱动级（DR），其可应用于提供取决于预定发射信号的预放大驱动信号（S DR）。功率放大器电路（DIPPA）还包括电耦合到驱动器级（DR）的频率选择器（DIP），并且可应用于将驱动器信号（S DR）分离成第一和第二信号（S1，S2））。第一信号（S_1）与第一预定相关联，第二信号（S_2）与第二预定频带相关联。功率放大器电路（DIPPA）至少包括第一和第二功率放大器级（PA1，PA2）。第一和第二功率放大器级（PA1，PA2）电耦合到频率选择器（DIP）。第一和第二功率放大器级（PA1，PA2）可分别根据第一和第二信号（S_1，S_2）分别提供第一和第二放大信号（S_A1，S_2）。

8. 发明申请

WO2010149629A1 LOW-CURRENT INPUT BUFFER 审中-公开
标题翻译：低电流输入缓冲器
公开(公告)号：WO2010149629A1
公开(公告)日：2010-12-29
申请号：PCT/EP2010/058743
申请日：2010-06-21
申请人： EPCOS AG , SPITS, Erwin , VAN DEN OEVER, Léon C. M.
发明人： SPITS, Erwin , VAN DEN OEVER, Léon C. M.
IPC分类号： H02H9/02 , H03K19/0185
CPC分类号： H03K19/018521
摘要： A current-limited differential entry stage compares an input signal (IN) to a reference voltage (V ref ) generated by a current-limited transistor or diode configuration (E6, E7). Current limiters comprise a D-mode feedback transistor (D2; D3) having a gate-source junction, the D-mode transistor not conducting between the source and the drain if a gate-source voltage is larger negative than a negative threshold voltage, and conducting between the source and the drain else,and a feedback connection (13; 23) connecting the source of the D- mode feedback transistor to its gate via a component that generates a voltage drop (E4, E5; E8, E9).
摘要翻译：电流限制差分输入级将输入信号（IN）与由限流晶体管或二极管配置（E6，E7）产生的参考电压（V ref）进行比较。电流限制器包括具有栅极 - 源极结的D型反馈晶体管（D2; D3），如果栅极 - 源极电压比负极性电压大负，则D模式晶体管不会在源极和漏极之间导通，以及在源极和漏极之间导通，以及通过产生电压降（E4，E5; E8，E9）的部件将D-模式反馈晶体管的源极连接到其栅极的反馈连接（13; 23）。

9. 发明申请

WO2010055102A1 P-TYPE FIELD-EFFECT TRANSISTOR AND METHOD OF PRODUCTION 审中-公开
标题翻译： P型场效应晶体管及其生产方法
公开(公告)号：WO2010055102A1
公开(公告)日：2010-05-20
申请号：PCT/EP2009/065067
申请日：2009-11-12
申请人： EPCOS AG , VAN DEN OEVER, Léon C. M.
发明人： VAN DEN OEVER, Léon C. M.
IPC分类号： H01L21/336 , H01L29/423 , H01L21/8252 , H01L27/06 , H01L29/20 , H01L29/205
CPC分类号： H01L29/4236 , H01L29/1087 , H01L29/20 , H01L29/205 , H01L29/66522 , H01L29/66621
摘要： An n-layer (3) is arranged above a substrate (1), which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode (10) into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric (6). Source/drain contacts (11) are electrically conductively connected with the portions of the p-layer.
摘要翻译： n层（3）布置在可以是GaAs的衬底（1）上方，并且p层（4）布置在n层上。 p层由栅电极（10）分离成形成源极和漏极的两个分开的部分。栅电极通过栅极电介质（6）与半导体材料绝缘。源极/漏极触点（11）与p层的部分导电连接。

10. 发明申请

WO2010046449A1 BIPOLAR TRANSISTOR WITH AN N-TYPE BASE AND METHOD OF PRODUCTION 审中-公开
标题翻译：具有N型基座的双极晶体管和生产方法
公开(公告)号：WO2010046449A1
公开(公告)日：2010-04-29
申请号：PCT/EP2009/063921
申请日：2009-10-22
申请人： EPCOS AG , VAN DEN OEVER, Léon C. M.
发明人： VAN DEN OEVER, Léon C. M.
IPC分类号： H01L29/417 , H01L29/47 , H01L29/73 , H01L29/735
CPC分类号： H01L29/7308 , H01L29/41708 , H01L29/475 , H01L29/735
摘要： A base contact connection (12), an emitter structure (4, 5) and a collector structure are arranged on an n-layer (3), which can be provided for additional npn transistors. The collector structure is arranged laterally to the emitter structure and at least one of the emitter and collector comprises a Schottky contact (14) on a surface area of the n-layer.
摘要翻译：基极接触连接（12），发射极结构（4,5）和集电极结构布置在n层（3）上，可以为附加的npn晶体管提供。集电极结构被布置在发射极结构的横向上，并且发射极和集电极中的至少一个包括在n层的表面区域上的肖特基接触（14）。

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