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1. 发明申请

WO2013148693A1 OFFLOAD PROCESSING OF DATA PACKETS 审中-公开
标题翻译：数据包的卸载处理
公开(公告)号：WO2013148693A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/033889
申请日：2013-03-26
申请人： EXEGY INCORPORATED , PARSONS, Scott , TAYLOR, David E. , INDECK, Ronald S.
发明人： PARSONS, Scott , TAYLOR, David E.
IPC分类号： H04L12/28
CPC分类号： G06Q40/04
摘要： Various techniques are disclosed for offloading the processing of data packets. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize data packets in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.
摘要翻译：公开了用于卸载数据分组的处理的各种技术。例如，可以通过卸载处理器处理输入数据分组，以生成以与输入数据分组不同的方式组织数据分组的输出数据分组的新流。此外，在示例性实施例中，卸载处理可以驻留在智能交换机中，诸如智能交换机，例如电子交易平台上游或下游的智能交换机。

2. 发明申请

WO2009089467A2 METHOD AND SYSTEM FOR LOW LATENCY BASKET CALCULATION 审中-公开
标题翻译：低延迟篮球计算的方法和系统
公开(公告)号：WO2009089467A2
公开(公告)日：2009-07-16
申请号：PCT/US2009/030623
申请日：2009-01-09
申请人： EXEGY INCORPORATED , TAYLOR, David, E. , SINGLA, Naveen , BRODIE, Benjamin, C. , MCVICAR, Nathaniel, S. , THIEL, Justin, R. , INDECK, Ronald, S.
发明人： TAYLOR, David, E. , SINGLA, Naveen , BRODIE, Benjamin, C. , MCVICAR, Nathaniel, S. , THIEL, Justin, R. , INDECK, Ronald, S.
IPC分类号： G06Q40/00 , G06F17/40 , G06F17/10
CPC分类号： G06Q40/00 , G06Q40/06
摘要： A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA).
摘要翻译：篮子计算引擎用于接收数据流并基于该数据加速篮子值的计算。在优选实施例中，篮子计算引擎用于处理金融市场数据以计算金融工具篮子的净资产值（NAV）。篮筐计算引擎可以部署在协处理器上并且也可以通过管线来实现，管线优选地包括篮子关联查找模块和篮子值更新模块。协处理器最好是可重新配置的逻辑设备，例如现场可编程门阵列（FPGA）。

3. 发明申请

WO2008154306A1 METHOD AND SYSTEM FOR HIGH SPEED OPTIONS PRICING 审中-公开
标题翻译：高速选项定价方法与系统
公开(公告)号：WO2008154306A1
公开(公告)日：2008-12-18
申请号：PCT/US2008/065955
申请日：2008-06-05
申请人： EXEGY INCORPORATED , SINGLA, Naveen , PARSONS, Scott , FRANKLIN, Mark, A. , TAYLOR, David, E.
发明人： SINGLA, Naveen , PARSONS, Scott , FRANKLIN, Mark, A. , TAYLOR, David, E.
IPC分类号： G06Q40/00
CPC分类号： G06Q40/04 , G06Q40/06
摘要： A high speed technique for options pricing in the financial industry is disclosed that can provide both high throughput and low latency. A parallel/pipelined architecture is disclosed for computing an implied volatility in connection with an option. Parallel/pipelined architectures are also disclosed for computing an option's theoretical fair price. Preferably these parallel/pipelined architectures are deployed in hardware, and more preferably reconfigurable logic such as Field Programmable Gate Arrays (FPGAs) to accelerate the options pricing operations relative to conventional software-based options pricing operations.
摘要翻译：披露了一种高速技术，可以提供高吞吐量和低延迟。公开了一种用于计算与选项有关的隐含波动率的并行/流水线架构。还披露了并行/流水线架构来计算期权的理论公平价格。优选地，这些并行/流水线架构部署在硬件中，并且更优选地可重新配置逻辑，例如现场可编程门阵列（FPGA），以相对于常规的基于软件的选项定价操作来加速选项定价操作。

4. 发明申请

WO2008157357A1 METHOD AND APPARATUS FOR HIGH SPEED PROCESSING OF FINANCIAL INFORMATION 审中-公开
标题翻译：金融信息高速处理的方法与装置
公开(公告)号：WO2008157357A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/066929
申请日：2008-06-13
申请人： EXEGY INCORPORATED , PARSONS, Scott , TAYLOR, David, E. , SCHUEHLER, David, Vincent , FRANKLIN, Mark, A. , CHAMBERLAIN, Roger, D.
发明人： PARSONS, Scott , TAYLOR, David, E. , SCHUEHLER, David, Vincent , FRANKLIN, Mark, A. , CHAMBERLAIN, Roger, D.
IPC分类号： G06Q40/00
CPC分类号： G06Q40/04 , G06Q40/00 , G06Q40/06
摘要： Methods and systems for processing financial market data using reconfigurable logic are disclosed. Various functional operations to be performed on the financial market data can be implemented in firmware pipelines to accelerate the speed of processing. Also, a combination of software logic and firmware logic can be used to efficiently control and manage the high speed flow of financial market data to and from the reconfigurable logic.
摘要翻译：公开了使用可重构逻辑来处理金融市场数据的方法和系统。可以在固件管道中实施对金融市场数据执行的各种功能操作，以加速处理速度。此外，可以使用软件逻辑和固件逻辑的组合来有效地控制和管理来自可重配置逻辑的金融市场数据的高速流。

5. 发明申请

WO2007121035A3 METHOD AND SYSTEM FOR HIGH THROUGHPUT BLOCKWISE INDEPENDENT ENCRYPTION/DECRYPTION 审中-公开
标题翻译：用于高速插入块独立加密/解码的方法和系统
公开(公告)号：WO2007121035A3
公开(公告)日：2008-09-18
申请号：PCT/US2007064712
申请日：2007-03-22
申请人： EXEGY INC , TAYLOR DAVID E , INDECK RONALD S , WHITE JASON R , CHAMBERLAIN ROGER D
发明人： TAYLOR DAVID E , INDECK RONALD S , WHITE JASON R , CHAMBERLAIN ROGER D
IPC分类号： H04L9/28 , H04K1/00 , H04K1/04 , H04K1/06
CPC分类号： H04L9/0637 , H04L9/0662 , H04L9/14 , H04L2209/125 , H04L2209/24
摘要： An encryption technique is disclosed for encrypting a data segment comprising a plurality of data blocks, wherein the security and throughput of the encryption is enhanced by using blockwise independent bit vectors for reversible combination with the data blocks prior to key encryption. Preferably, the blockwise independent bit vectors are derived from a data tag associated with the data segment. Several embodiments are disclosed for generating these blockwise independent bit vectors. In a preferred embodiment, the data tag comprises a logical block address (LBA) for the data segment. Also disclosed herein is a corresponding decryption technique as well as a corresponding symmetrical encryption/decryption technique.
摘要翻译：公开了一种用于加密包括多个数据块的数据段的加密技术，其中通过在密钥加密之前使用与数据块可逆组合的块独立比特向量来增强加密的安全性和吞吐量。优选地，从与数据段相关联的数据标签导出块独立比特向量。公开了用于产生这些块独立比特向量的几个实施例。在优选实施例中，数据标签包括用于数据段的逻辑块地址（LBA）。这里也公开了相应的解密技术以及对应的对称加密/解密技术。

6. 发明申请

WO2007121035A2 METHOD AND SYSTEM FOR HIGH THROUGHPUT BLOCKWISE INDEPENDENT ENCRYPTION/DECRYPTION 审中-公开
标题翻译：用于高速插入块独立加密/解码的方法和系统
公开(公告)号：WO2007121035A2
公开(公告)日：2007-10-25
申请号：PCT/US2007/064712
申请日：2007-03-22
申请人： EXEGY INCORPORATED , TAYLOR, David E. , INDECK, Ronald S. , WHITE, Jason R. , CHAMBERLAIN, Roger D.
发明人： TAYLOR, David E. , INDECK, Ronald S. , WHITE, Jason R. , CHAMBERLAIN, Roger D.
IPC分类号： H04L9/28 , H04K1/06 , H04L9/00 , H04K1/04 , H04K1/00
CPC分类号： H04L9/0637 , H04L9/0662 , H04L9/14 , H04L2209/125 , H04L2209/24
摘要： An encryption technique is disclosed for encrypting a data segment comprising a plurality of data blocks, wherein the security and throughput of the encryption is enhanced by using blockwise independent bit vectors for reversible combination with the data blocks prior to key encryption. Preferably, the blockwise independent bit vectors are derived from a data tag associated with the data segment. Several embodiments are disclosed for generating these blockwise independent bit vectors. In a preferred embodiment, the data tag comprises a logical block address (LBA) for the data segment. Also disclosed herein is a corresponding decryption technique as well as a corresponding symmetrical encryption/decryption technique.
摘要翻译：公开了一种用于加密包括多个数据块的数据段的加密技术，其中通过在密钥加密之前使用与数据块可逆组合的块独立比特向量来增强加密的安全性和吞吐量。优选地，从与数据段相关联的数据标签导出块独立位向量。公开了用于生成这些块独立比特向量的几个实施例。在优选实施例中，数据标签包括用于数据段的逻辑块地址（LBA）。本文还公开了相应的解密技术以及相应的对称加密/解密技术。

7. 发明申请

WO2009029842A1 METHOD AND APPARATUS FOR HARDWARE-ACCELERATED ENCRYPTION/DECRYPTION 审中-公开
标题翻译：用于硬件加速加密/分解的方法和装置
公开(公告)号：WO2009029842A1
公开(公告)日：2009-03-05
申请号：PCT/US2008/074862
申请日：2008-08-29
申请人： EXEGY INCORPORATED , TAYLOR, David, E. , THURMON, Brandon, Parks , INDECK, Ronald, S.
发明人： TAYLOR, David, E. , THURMON, Brandon, Parks , INDECK, Ronald, S.
IPC分类号： H04L9/00
CPC分类号： H04L9/0861 , H04L9/0618 , H04L9/0819 , H04L9/0822 , H04L9/0844 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： An integrated circuit for data encryption/decryption and secure key management is disclosed. The integrated circuit may be used in conjunction with other integrated circuits, processors, and software to construct a wide variety of secure data processing, storage, and communication systems. One embodiment of the integrated circuit includes a symmetric block cipher that may be scaled to strike a favorable balance among processing throughput and power consumption. The modular architecture supports multiple encryption modes and key management functions. The integrated circuit may also include a key management processor that can be programmed to support a wide variety of asymmetric key cryptography functions for secure key exchange with remote key storage devices and enterprise key management servers. Internal data and key buffers enable the device to re-key encrypted data without exposing data. The key management functions allow the device to function as a cryptographic domain bridge in a federated architecture
摘要翻译：公开了用于数据加密/解密和安全密钥管理的集成电路。集成电路可以与其他集成电路，处理器和软件结合使用，以构建各种各样的安全数据处理，存储和通信系统。集成电路的一个实施例包括可以被缩放以在处理吞吐量和功耗之间达到有利平衡的对称分组密码。模块化架构支持多种加密模式和密钥管理功能。集成电路还可以包括密钥管理处理器，其可以被编程为支持用于与远程密钥存储设备和企业密钥管理服务器的安全密钥交换的各种不对称密钥密码术功能。内部数据和密钥缓冲器可使设备重新加密加密数据，而不会暴露数据。密钥管理功能允许设备在联合架构中用作加密域桥

8. 发明申请

WO2009089467A3 METHOD AND SYSTEM FOR LOW LATENCY BASKET CALCULATION 审中-公开
标题翻译：低年龄篮子计算方法与系统
公开(公告)号：WO2009089467A3
公开(公告)日：2009-12-30
申请号：PCT/US2009030623
申请日：2009-01-09
申请人： EXEGY INC , TAYLOR DAVID E , SINGLA NAVEEN , BRODIE BENJAMIN C , MCVICAR NATHANIEL S , THIEL JUSTIN R , INDECK RONALD S
发明人： TAYLOR DAVID E , SINGLA NAVEEN , BRODIE BENJAMIN C , MCVICAR NATHANIEL S , THIEL JUSTIN R , INDECK RONALD S
IPC分类号： G06Q40/00
CPC分类号： G06Q40/00 , G06Q40/06
摘要： A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA).
摘要翻译：部署篮子计算引擎以接收数据流，并基于该数据加速计算篮值。在优选实施例中，篮子计算引擎用于处理金融市场数据以计算金融工具篮子的净资产值（NAV）。篮子计算引擎可以部署在协处理器上，并且也可以通过管道实现，管线优选地包括篮关联查找模块和篮值更新模块。协处理器优选地是诸如现场可编程门阵列（FPGA）的可重新配置的逻辑器件。

9. 发明申请

WO2008063973A3 METHOD AND SYSTEM FOR HIGH PERFORMANCE DATA METATAGGING AND DATA INDEXING USING COPROCESSORS 审中-公开
公开(公告)号：WO2008063973A3
公开(公告)日：2008-05-29
申请号：PCT/US2007/084464
申请日：2007-11-12
申请人： EXEGY INCORPORATED , INDECK, Ronald S. , SINGLA, Naveen , TAYLOR, David E.
发明人： INDECK, Ronald S. , SINGLA, Naveen , TAYLOR, David E.
IPC分类号： G06F7/00 , G06F15/16
摘要： Disclosed herein is a method and system for hardware-accelerating the generation of metadata for a data stream using a coprocessor (450). Using these techniques, data can be richly indexed, classified, and clustered at high speeds. Reconfigurable logic (402) such a field programmable gate arrays (FPGAs) can be used by the coprocessor for this hardware acceleration. Techniques such as exact matching, approximate matching, and regular expression pattern matching can be employed by the coprocessor to generate desired metadata for the data stream.

10. 发明申请

WO2008063973A2 METHOD AND SYSTEM FOR HIGH PERFORMANCE DATA METATAGGING AND DATA INDEXING USING COPROCESSORS 审中-公开
标题翻译：用于高性能数据分类和使用协处理器的数据索引的方法和系统
公开(公告)号：WO2008063973A2
公开(公告)日：2008-05-29
申请号：PCT/US2007084464
申请日：2007-11-12
申请人： EXEGY INC , INDECK RONALD S , SINGLA NAVEEN , TAYLOR DAVID E
发明人： INDECK RONALD S , SINGLA NAVEEN , TAYLOR DAVID E
IPC分类号： G06F17/30
CPC分类号： G06F17/30943
摘要： Disclosed herein is a method and system for hardware-accelerating the generation of metadata for a data stream using a coprocessor. Using these techniques, data can be richly indexed, classified, and clustered at high speeds. Reconfigurable logic such a field programmable gate arrays (FPGAs) can be used by the coprocessor for this hardware acceleration. Techniques such as exact matching, approximate matching, and regular expression pattern matching can be employed by the coprocessor to generate desired metadata for the data stream.
摘要翻译：这里公开了一种用于硬件加速使用协处理器为数据流生成元数据的方法和系统。使用这些技术，数据可以高速索引，分类和集群。协调处理器可以使用这种现场可编程门阵列（FPGA）的可重构逻辑来进行该硬件加速。协处理器可以采用诸如精确匹配，近似匹配和正则表达式模式匹配的技术来生成用于数据流的期望的元数据。

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