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1. 发明申请

WO2007018850A3 FABRICATION OF THREE DIMENSIONAL INTEGRATED CIRCUIT EMPLOYING MULTIPLE DIE PANELS 审中-公开
标题翻译：使用多个DIE面板的三维集成电路的制造
公开(公告)号：WO2007018850A3
公开(公告)日：2008-01-03
申请号：PCT/US2006026256
申请日：2006-07-03
申请人： FREESCALE SEMICONDUCTOR INC , JONES ROBERT E , POZDER SCOTT K
发明人： JONES ROBERT E , POZDER SCOTT K
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/50 , B32B37/00 , H01L22/20 , Y10T156/10 , Y10T156/1052 , Y10T156/1062
摘要： A method of assembling an electronic device includes testing (602) a first wafer (100) of first die to identify the location of functional first die and dividing (604) the first wafer (100) into a set of panels (104-1, 104-2, 104-3), wherein a panel includes an MxN array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an MxN array of second die in the second wafer. The panel stack is sawed (606) into a devices comprising a first die bonded to a second die. Dividing the first (100) wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.
摘要翻译：组装电子设备的方法包括：测试（602）第一晶片的第一晶片（100）以识别功能第一裸片的位置，并将第一晶片（100）分成（604）成一组面板（104-1， 104-2,104-3），其中面板包括第一管芯的M×N阵列。面板结合到第二晶片的面板部位以形成面板堆叠，其中面板部位在第二晶片中限定第二模具的MxN阵列。面板堆叠被锯切（606）成包括结合到第二模具的第一模具的装置。将第一（100）晶片分成面板可以静态或动态地进行（以使产量超过特定阈值的面板的数量最大化）。可以执行根据功能性模具图案的面板和面板位置的分层以优先地将面板粘合到同一箱的面板位置。

2. 发明申请

WO2007035234A3 SEMICONDUCTOR STACKED DIE/WAFER CONFIGURATION AND PACKAGING AND METHOD THEREOF 审中-公开
标题翻译：半导体堆叠DIE / WAFER配置及其包装及其方法
公开(公告)号：WO2007035234A3
公开(公告)日：2007-12-06
申请号：PCT/US2006034319
申请日：2006-08-30
申请人： FREESCALE SEMICONDUCTOR INC , POZDER SCOTT K , ALAM SYED M , JONES ROBERT E
发明人： POZDER SCOTT K , ALAM SYED M , JONES ROBERT E
IPC分类号： H01L21/00
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541
摘要： A reciprocal design symmetry allows stacked wafers (120, 122) or die (154) on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect (270-279, 89-80) required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.
摘要翻译：互易设计对称性允许晶片上的堆叠晶片（120,122）或裸片（154）使用仅仅由几层（例如金属互连层）变化的相同设计或设计。翻转或旋转一个管芯或晶片允许堆叠的管芯相对于彼此具有往复的取向，其可用于减小垂直堆叠的管芯和/或晶片之间所需的互连（270-279,88-80）。当晶片和/或管芯堆叠时，翻转和/或旋转也可用于改善散热。然后可以包装堆叠的晶片或管芯。

3. 发明申请

WO2004073014A3 METAL REDUCTION IN WAFER SCRIBE AREA 审中-公开
公开(公告)号：WO2004073014A3
公开(公告)日：2004-08-26
申请号：PCT/US2004/001925
申请日：2004-01-23
申请人： FREESCALE SEMICONDUCTOR, INC. , POZDER, Scott, K. , UEHLING, Trent, S. , RAMANATHAN, Lakshmi, N.
发明人： POZDER, Scott, K. , UEHLING, Trent, S. , RAMANATHAN, Lakshmi, N.
IPC分类号： H01L21/301
摘要： A process for removing metal from a scribe area 103 of a semiconductor wafer 101. The metal removed may include exposed metal in a saw path 111 of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer 203 on the wafer surface. Removal of the metal in the saw path 111 may reduce the amount of metal buildup on a saw blade 903 during singulation of the die areas 1007 of a wafer.

4. 发明申请

WO2007130731A3 BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS 审中-公开
标题翻译：用于三维集成电路的障碍
公开(公告)号：WO2007130731A3
公开(公告)日：2008-09-18
申请号：PCT/US2007062538
申请日：2007-02-22
申请人： FREESCALE SEMICONDUCTOR INC , POZDER SCOTT K , MICHAELSON LYNNE M , MATHEW VARUGHESE
发明人： POZDER SCOTT K , MICHAELSON LYNNE M , MATHEW VARUGHESE
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76898 , H01L21/76805 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/50 , H01L27/0688 , H01L2224/83191 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/14 , H01L2924/00
摘要： A method for forming a semiconductor device (30) includes providing a first integrated circuit (10) having a landing pad (24) and attaching a second integrated circuit to the first integrated circuit (10) using at least one bonding layer (42). The second integrated circuit has an inter-circuit trace (38), the inter-circuit trace (38) has an inter-circuit trace opening (40). The method further includes forming an opening (58) through the second integrated circuit, the opening (58) extending through the inter-circuit trace opening, forming a selective barrier (52) on exposed portions of the inter-circuit trace in the opening (58), extending the opening (58) through the at least one bonding layer (42) to the landing pad (24), and filling the opening (58) with a conductive fill material (64). The selective barrier layer (52) comprises at least one of cobalt or nickel, and the conductive fill material (64) electrically connects the inter-circuit trace (38) and the landing pad (24).
摘要翻译：一种用于形成半导体器件（30）的方法包括提供具有着陆焊盘（24）的第一集成电路（10），并且使用至少一个结合层（42）将第二集成电路附接到第一集成电路（10）。第二集成电路具有电路间迹线（38），电路间迹线（38）具有电路间迹线开口（40）。该方法还包括形成穿过第二集成电路的开口（58），该开口（58）延伸穿过该回路迹线开口，在该开口中的该电路间迹线的暴露部分上形成选择性屏障（52） 58），使开口（58）穿过所述至少一个结合层（42）延伸到所述着陆垫（24），以及用导电填充材料（64）填充所述开口（58）。选择性阻挡层（52）包括钴或镍中的至少一种，并且导电填充材料（64）电连接电路间迹线（38）和着陆焊盘（24）。

5. 发明申请

WO2006076083A2 INTEGRATED CIRCUIT HAVING STRUCTURAL SUPPORT FOR A FLIP-CHIP INTERCONNECT PAD AND METHOD THEREFOR 审中-公开
标题翻译：具有FLIP-CHIP INTERCONNECT PAD的结构支持的集成电路及其方法
公开(公告)号：WO2006076083A2
公开(公告)日：2006-07-20
申请号：PCT/US2005043220
申请日：2005-11-30
申请人： FREESCALE SEMICONDUCTOR INC , POZDER SCOTT K , HESS KEVIN J , LEUNG PAK K , TRAVIS EDWARD O , WILKERSON BRETT P , WONTOR DAVID G , ZHAO JIE-HUA
发明人： POZDER SCOTT K , HESS KEVIN J , LEUNG PAK K , TRAVIS EDWARD O , WILKERSON BRETT P , WONTOR DAVID G , ZHAO JIE-HUA
IPC分类号： H01L21/4763
CPC分类号： H01L24/10 , H01L23/522 , H01L24/02 , H01L24/13 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.
摘要翻译：减轻施加到接合焊盘（32）的应力引起的缺陷的问题的技术包括：在实际制造集成电路（10）之前，将互连层（18,22,26）中的虚设金属线（74,76）以增加互连层的金属密度。当互连层之间的层间电介质（16,20,24）为低k材料时，这些问题更有可能。在每个接合垫周围和之下的临界区域或力区域（64）限定了由于与该接合焊盘的接触而可能发生缺陷的区域。金属密度低于某一百分比的这样关键区域中的任何互连层可能是互连层中缺陷的原因。在临界区域中具有低于该百分比的金属密度的任何互连层都添加有虚拟金属线。

6. 发明申请

WO2005052990A3 SEMICONDUCTOR DEVICE WITH MAGNETICALY PERMEABLE HEAT SINK 审中-公开
标题翻译：具有磁性可渗透热沉的半导体器件
公开(公告)号：WO2005052990A3
公开(公告)日：2005-07-07
申请号：PCT/US2004035183
申请日：2004-10-22
申请人： FREESCALE SEMICONDUCTOR INC , POZDER SCOTT K , RASCO MICHELLE F
发明人： POZDER SCOTT K , RASCO MICHELLE F
IPC分类号： G11C11/16 , H01L20060101 , H01L21/44 , H01L21/58 , H01L21/60 , H01L23/06 , H01L23/10 , H01L23/14 , H01L23/48 , H01L23/552
CPC分类号： H01L23/552 , G11C11/16 , H01L23/14 , H01L24/27 , H01L24/29 , H01L24/83 , H01L2224/16 , H01L2224/274 , H01L2224/2919 , H01L2224/29198 , H01L2224/29499 , H01L2224/73253 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor device (16) is attached to a heat sink (22) by glue (20) that is both thermally conductive and magnetically permeable. The glue fills different features in the surface of the semiconductor device (16) so that there is good coupling between the semiconductor device (16) and the heat sink. The glue (20) is filled with magnetic particles so that the glue (20) is magnetically permeable. The semiconductor device (16) is formed with the heat sink (22) at the wafer level and then singulated after attachment of the heat sink (22) with the glue (20).
摘要翻译：半导体器件（16）通过既导热又可导磁的胶水（20）附着到散热器（22）。胶水填充半导体器件（16）表面中的不同特征，使得半导体器件（16）和散热器之间具有良好的耦合。胶水（20）填充有磁性颗粒，使得胶水（20）是磁性可渗透的。半导体器件（16）在晶片级上形成有散热器（22），然后在散热器（22）与粘合剂（20）附着之后被分离。

7. 发明申请

WO2009085609A3 3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD 审中-公开
公开(公告)号：WO2009085609A3
公开(公告)日：2009-07-09
申请号：PCT/US2008/086174
申请日：2008-12-10
申请人： FREESCALE SEMICONDUCTOR INC. , POZDER, Scott K. , CHATTERJEE, Ritwik
发明人： POZDER, Scott K. , CHATTERJEE, Ritwik
IPC分类号： H01L23/12 , H01L21/60 , H01L23/48
摘要： A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.

8. 发明申请

WO2007143269A1 DIE LEVEL METAL DENSITY GRADIENT FOR IMPROVED FLIP CHIP PACKAGE RELIABILITY 审中-公开
标题翻译： DIE级金属密度梯度用于改进的片状芯片包装可靠性
公开(公告)号：WO2007143269A1
公开(公告)日：2007-12-13
申请号：PCT/US2007/065617
申请日：2007-03-30
申请人： FREESCALE SEMICONDUCTOR INC. , POZDER, Scott, K. , HESS, Kevin, J. , TIAN, Ruiqi , TRAVIS, Edward, O. , UEHLING, Trent, S. , WILKERSON, Brett, P. , YU, Katie, C.
发明人： POZDER, Scott, K. , HESS, Kevin, J. , TIAN, Ruiqi , TRAVIS, Edward, O. , UEHLING, Trent, S. , WILKERSON, Brett, P. , YU, Katie, C.
IPC分类号： H01L21/76
CPC分类号： H01L21/76838 , H01L24/13 , H01L24/14 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/13006 , H01L2224/13022 , H01L2224/13076 , H01L2224/13111 , H01L2224/13147 , H01L2224/13171 , H01L2224/13181 , H01L2224/13184 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： An integrated circuit (11) has metal bumps (80) on the top surface that create a potentially destructive stress on the underlying layers (91-97) when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers (91, 93, 95, 97) has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer (91, 93, 95, 97 generally under the metal bump (80) require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers (95, 97) that are further from the surface of the integrated circuit (11). The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.
摘要翻译：集成电路（11）在顶表面上具有金属凸块（80），当形成金属凸块时，其在下面的层（91-97）上产生潜在的破坏性应力。确保在下面的金属互连层（91,93,95,97）中的最小金属浓度被实现以减少破坏效应。角落中最低的金属浓度最高，接下来沿边界不在角落，接下来是内部。互连层（91,93,95,97）中通常在金属凸块（80）下方的区域需要比不在凸块下方的相邻区域更多的浓度。对于进一步的金属互连层（95,97）需要较小的浓度通过首先尝试相对简单的解决方案实现所需的金属浓度，如果没有效果，则尝试不同的方法，直到达到最小浓度，或直到最后一次尝试。

9. 发明申请

WO2007035234A2 SEMICONDUCTOR STACKED DIE/WAFER CONFIGURATION AND PACKAGING AND METHOD THEREOF 审中-公开
标题翻译：半导体堆叠的模片/晶片配置和包装及其方法
公开(公告)号：WO2007035234A2
公开(公告)日：2007-03-29
申请号：PCT/US2006/034319
申请日：2006-08-30
申请人： FREESCALE SEMICONDUCTOR , POZDER, Scott, K. , ALAM, Syed, M. , JONES, Robert, E.
发明人： POZDER, Scott, K. , ALAM, Syed, M. , JONES, Robert, E.
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541
摘要： A reciprocal design symmetry allows stacked wafers (120, 122) or die (154) on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect (270-279, 89-80) required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.
摘要翻译：对等设计对称性允许晶片上的堆叠晶片（120,122）或裸片（154）使用仅通过少数层改变的相同设计或设计（例如金属互连层）。翻转或旋转一个管芯或晶片允许堆叠管芯相对于彼此具有相互取向，这可用于减少垂直堆叠的管芯和/或晶片之间所需的互连（270-279,89-80）。翻转和/或旋转也可以用于在晶片和/或管芯堆叠时改善散热。然后可以将堆叠的晶圆或模具包装起来。

10. 发明申请

WO2007018850A2 FABRICATION OF THREE DIMENSIONAL INTEGRATED CIRCUIT EMPLOYING MULTIPLE DIE PANELS 审中-公开
标题翻译：使用多个DIE面板的三维集成电路的制造
公开(公告)号：WO2007018850A2
公开(公告)日：2007-02-15
申请号：PCT/US2006/026256
申请日：2006-07-03
申请人： FREESCALE SEMICONDUCTOR , JONES, Robert E. , POZDER, Scott K.
发明人： JONES, Robert E. , POZDER, Scott K.
IPC分类号： B32B37/00 , B32B38/04 , H01L21/30
CPC分类号： H01L21/50 , B32B37/00 , H01L22/20 , Y10T156/10 , Y10T156/1052 , Y10T156/1062
摘要： A method of assembling an electronic device includes testing (602) a first wafer (100) of first die to identify the location of functional first die and dividing (604) the first wafer (100) into a set of panels (104-1, 104-2, 104-3), wherein a panel includes an MxN array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an MxN array of second die in the second wafer. The panel stack is sawed (606) into a devices comprising a first die bonded to a second die. Dividing the first (100) wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.
摘要翻译：一种组装电子设备的方法包括：测试（602）第一晶片的第一晶片（100）以识别功能第一裸片的位置，并将第一晶片（100）分成（604）成一组面板（104-1， 104-2,104-3），其中面板包括第一管芯的M×N阵列。面板结合到第二晶片的面板位置以形成面板堆叠，其中面板位置在第二晶片中限定第二模具的MxN阵列。面板堆叠被锯切（606）成包括结合到第二模具的第一模具的装置。将第一（100）晶片分成面板可以静态或动态地进行（以使产量超过特定阈值的面板数量最大化）。可以执行根据功能性模具图案的面板和面板位置的分层以将面板优先地连接到同一箱的面板位置。

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