专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006005025A3 THREAD-BASED CLOCK ENABLING IN A MULTI-THREADED PROCESSOR 审中-公开
标题翻译：基于螺纹的时钟启用在多线程处理器中
公开(公告)号：WO2006005025A3
公开(公告)日：2007-01-25
申请号：PCT/US2005023647
申请日：2005-06-30
申请人： SUN MICROSYSTEMS INC , GOLLA ROBERT T , BROOKS JEFFREY S , OLSON CHRISTOPHER H
发明人： GOLLA ROBERT T , BROOKS JEFFREY S , OLSON CHRISTOPHER H
IPC分类号： G06F9/38 , G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G06F9/3851 , Y02D10/128 , Y02D10/171
摘要： A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.
摘要翻译：一种用于控制多线程处理器中的功耗的方法和装置。在一个实施例中，处理器包括用于处理指令的至少一个逻辑单元。逻辑单元包括多个位置，其中多个位置中的每一个对应于至少一个指令线程。时钟信号可以经由时钟门控单元提供给逻辑单元。时钟门控单元被配置为当没有指令线程对于该位置有效时，禁止将时钟信号提供给相应的一个线程位置。禁止线程位置的时钟信号的抑制可能会降低处理器的功耗。

2. 发明申请

WO2005008956A1 METHOD AND APPARATUS FOR FAST RC4-LIKE ENCRYPTION 审中-公开
标题翻译：快速RC4加密的方法和装置
公开(公告)号：WO2005008956A1
公开(公告)日：2005-01-27
申请号：PCT/US2004/022248
申请日：2004-07-09
申请人： SUN MICROSYSTEMS, INC. , RARICK, Leonard, D. , OLSON, Christopher, H.
发明人： RARICK, Leonard, D. , OLSON, Christopher, H.
IPC分类号： H04L9/18
CPC分类号： H04L9/065 , H04L2209/125
摘要： A method and apparatus for encrypting information according to the RC4 algorithm. In one embodiment, a method for encrypting information includes obtaining a value S’i! from an array having a plurality of values and determining a value S’j! based on the value S’i! in a first pipeline stage. In a second pipeline stage, a byte V of the keystreams may be determined from the value S’i! and the value S’j!. The value V may then be exclusive ORed (XORed) with a data value that forms a portion of the information being encrypted. A first logic unit may include the first pipeline stage, while a second logic unit may include the second pipeline stage. The array may be stored in a plurality of flip-flops in one embodiment, or may be stored in one or more register files in a second embodiment. The method and apparatus may be used for decrypting information as well.
摘要翻译：一种根据RC4算法加密信息的方法和装置。在一个实施例中，一种用于加密信息的方法包括获得值S'i！从具有多个值的阵列确定值S'j！基于S'i的价值！在第一个流水线阶段。在第二流水线阶段，密钥流的字节V可以从值S'i确定。和值S'j！然后，值V可以与形成被加密的信息的一部分的数据值异或（异或）。第一逻辑单元可以包括第一流水线级，而第二逻辑单元可以包括第二流水线级。在一个实施例中，阵列可以存储在多个触发器中，或者可以在第二实施例中存储在一个或多个寄存器文件中。该方法和装置也可用于解密信息。

3. 发明申请

WO2006005025A2 THREAD-BASED CLOCK ENABLING IN A MULTI-THREADED PROCESSOR 审中-公开
标题翻译：基于螺纹的时钟在多线程处理器中启用
公开(公告)号：WO2006005025A2
公开(公告)日：2006-01-12
申请号：PCT/US2005/023647
申请日：2005-06-30
申请人： SUN MICROSYSTEMS, INC. , GOLLA, Robert, T. , BROOKS, Jeffrey, S. , OLSON, Christopher, H.
发明人： GOLLA, Robert, T. , BROOKS, Jeffrey, S. , OLSON, Christopher, H.
IPC分类号： G06F9/38
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G06F9/3851 , Y02D10/128 , Y02D10/171
摘要： A method and apparatus for controlling power consumption in a multi-threaded processor. In one embodiment, the processor includes at least one logic unit for processing instructions. The logic unit includes a plurality of positions, wherein each of the plurality of positions corresponds to at least one instruction thread. Clock signals may be provided to the logic unit via a clock gating unit. The clock gating unit is configured to inhibit a clock signal from being provided to a corresponding one of the thread positions when no instruction thread is active for that position. The inhibiting of the clock signal for an inactive thread position may reduce power consumption by the processor.
摘要翻译：一种用于控制多线程处理器中的功耗的方法和装置。在一个实施例中，处理器包括用于处理指令的至少一个逻辑单元。逻辑单元包括多个位置，其中多个位置中的每一个对应于至少一个指令线程。时钟信号可以经由时钟门控单元提供给逻辑单元。时钟门控单元被配置为当没有指令线程对于该位置有效时，禁止将时钟信号提供给相应的一个线程位置。禁止线程位置的时钟信号可能会降低处理器的功耗。

4. 发明申请

WO2012158633A1 SUPPRESSION OF CONTROL TRANSFER INSTRUCTIONS ON INCORRECT SPECULATIVE EXECUTION PATHS 审中-公开
标题翻译：禁止不正当执行执行机构的控制转移指令
公开(公告)号：WO2012158633A1
公开(公告)日：2012-11-22
申请号：PCT/US2012/037813
申请日：2012-05-14
申请人： ORACLE INTERNATIONAL CORPORATION , OLSON, Christopher, H. , SHAH, Manish, K.
发明人： OLSON, Christopher, H. , SHAH, Manish, K.
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3842 , G06F9/3844 , G06F9/3861
摘要： Techniques are disclosed relating to a processor that is configured to execute control transfer instructions (CTIs). In some embodiments, the processor includes a mechanism that suppresses results of mispredicted younger CTIs on a speculative execution path. This mechanism permits the branch predictor to maintain its fidelity, and eliminates spurious flushes of the pipeline. In one embodiment, a misprediction bit is be used to indicate that a misprediction has occurred, and younger CTIs than the CTI that was mispredicted are suppressed. In some embodiments, the processor may be configured to execute instruction streams from multiple threads. Each thread may include a misprediction indication. CTIs in each thread may execute in program order with respect to other CTIs of the thread, while instructions other than CTIs may execute out of program order.
摘要翻译：公开了涉及被配置为执行控制传送指令（CTI）的处理器的技术。在一些实施例中，处理器包括抑制推测性执行路径上的错误的较新CTI的结果的机制。这种机制允许分支预测器保持其保真度，并且消除管道的杂散冲洗。在一个实施例中，错误预测位用于指示发生了错误预测，并且抑制了比错误预测的CTI更年轻的CTI。在一些实施例中，处理器可以被配置为执行来自多个线程的指令流。每个线程可以包括错误预测指示。每个线程中的CTI可以以相对于线程的其他CTI的程序顺序执行，而除了CTI之外的指令可以执行程序顺序。

5. 发明申请

WO2012158629A1 BRANCH TARGET STORAGE AND RETRIEVAL IN AN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：分支目标存储和在订单处理器中的检索
公开(公告)号：WO2012158629A1
公开(公告)日：2012-11-22
申请号：PCT/US2012/037807
申请日：2012-05-14
申请人： ORACLE INTERNATIONAL CORPORATION , OLSON, Christopher, H. , SHAH, Manish, K.
发明人： OLSON, Christopher, H. , SHAH, Manish, K.
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3808 , G06F9/3844
摘要： A processor configured to facilitate transfer and storage of predicted targets for control transfer instructions (CTIs). In certain embodiments, the processor may be multithreaded and support storage of predicted targets for multiple threads. In some embodiments, a CTI branch target may be stored by one element of a processor and a tag may indicate the location of the stored target. The tag may be associated with the CTI rather than associating the complete target address with the CTI. When the CTI reaches an execution stage of the processor, the tag may be used to retrieve the predicted target address. In some embodiments using a tag to retrieve a predicted target, CTI instructions from different processor threads may be interleaved without affecting retrieval of predicted targets.
摘要翻译：处理器，被配置为便于传送和存储用于控制传输指令（CTI）的预测目标。在某些实施例中，处理器可以是多线程的并且支持对多个线程的预测目标的存储。在一些实施例中，CTI分支目标可以由处理器的一个元件存储，并且标签可以指示所存储的目标的位置。标签可能与CTI相关联，而不是将完整的目标地址与CTI相关联。当CTI到达处理器的执行阶段时，该标签可用于检索预测的目标地址。在使用标签来检索预测目标的一些实施例中，来自不同处理器线程的CTI指令可以被交错而不影响预测目标的检索。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式