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1. 发明申请

WO2005117027A1 REPAIR OF MEMORY CELLS 审中-公开
标题翻译：记忆细胞修复
公开(公告)号：WO2005117027A1
公开(公告)日：2005-12-08
申请号：PCT/US2005/016718
申请日：2005-05-12
申请人： ANALOG DEVICES, INC. , MIKOL, Gregory, P.
发明人： MIKOL, Gregory, P.
IPC分类号： G11C29/00
CPC分类号： G11C29/846 , G11C29/806 , G11C29/808
摘要： A memory device has at least one sub array (206, 208, 210, 212) of memory cells having data columns and at least one spare sub array (202, 204) having spare columns. In one embodiment the sub array of memory cells and the sub array having spare columns are the same sub array. Individual elements in the sub arrays of memory cells can be repaired using an individual element from the spare sub array.
摘要翻译：存储器件具有至少一个具有数据列的存储器单元的子阵列（206,208,210,212）以及具有备用列的至少一个备用子阵列（202,204）。在一个实施例中，存储器单元的子阵列和具有备用列的子阵列是相同的子阵列。可以使用备用子阵列中的单个元素修复存储器单元的子阵列中的各个元素。

2. 发明申请

WO2008121426A2 TESTING FOR SRAM MEMORY DATA RETENTION 审中-公开
标题翻译：用于SRAM存储器数据保留的测试
公开(公告)号：WO2008121426A2
公开(公告)日：2008-10-09
申请号：PCT/US2008/051592
申请日：2008-01-22
申请人： ANALOG DEVICES, INC. , EBY, Michael, D. , MIKOL, Gregory, P. , DEMARIS, James, E.
发明人： EBY, Michael, D. , MIKOL, Gregory, P. , DEMARIS, James, E.
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50016
摘要： A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.
摘要翻译：测试存储器单元的方法包括产生逻辑低信号，产生逻辑高信号，将逻辑高电平信号降低到与逻辑低电平信号相加的电平加偏移以产生降低的逻辑高电平信号，提供逻辑低电平信号并且将降低的逻辑高信号传送到存储器单元，允许存储器单元实现存储器状态，以及测试存储器单元以确定存储器状态是否是期望的存储器状态。存储器阵列具有存储块阵列，用于向存储块阵列提供写入数据的写选择电路，以及数据保持测试电路，用于将具有与逻辑高对应的电平的写入数据减少至对应于逻辑的电平低加偏移。

3. 发明申请

WO2008121426A3 TESTING FOR SRAM MEMORY DATA RETENTION 审中-公开
标题翻译：用于SRAM存储器数据保留的测试
公开(公告)号：WO2008121426A3
公开(公告)日：2009-01-15
申请号：PCT/US2008051592
申请日：2008-01-22
申请人： ANALOG DEVICES INC , EBY MICHAEL D , MIKOL GREGORY P , DEMARIS JAMES E
发明人： EBY MICHAEL D , MIKOL GREGORY P , DEMARIS JAMES E
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50016
摘要： A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.
摘要翻译：测试存储器单元的方法包括产生逻辑低信号，产生逻辑高信号，将逻辑高电平信号降低到与逻辑低电平信号相加的电平加偏移以产生降低的逻辑高电平信号，提供逻辑低电平信号并且将降低的逻辑高信号传送到存储器单元，允许存储器单元实现存储器状态，以及测试存储器单元以确定存储器状态是否是预期的存储器状态。存储器阵列具有存储块阵列，用于向存储块阵列提供写入数据的写选择电路，以及数据保持测试电路，用于将具有与逻辑高对应的电平的写入数据减少至对应于逻辑的电平低加偏移。

4. 发明申请

WO2008121426A9 TESTING FOR SRAM MEMORY DATA RETENTION 审中-公开
标题翻译：测试SRAM存储器数据保留
公开(公告)号：WO2008121426A9
公开(公告)日：2008-11-27
申请号：PCT/US2008051592
申请日：2008-01-22
申请人： ANALOG DEVICES INC , EBY MICHAEL D , MIKOL GREGORY P , DEMARIS JAMES E
发明人： EBY MICHAEL D , MIKOL GREGORY P , DEMARIS JAMES E
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50016
摘要： A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.
摘要翻译：一种测试存储器单元的方法包括产生逻辑低信号，产生逻辑高信号，将逻辑高信号减小到对应于逻辑低信号加上偏移的电平以产生减小的逻辑高信号，提供逻辑低信号以及降低的逻辑高信号到存储器单元，从而允许存储器单元实现存储器状态，并且测试存储器单元以确定存储器状态是否是预期的存储器状态。存储器阵列具有存储器块阵列，向存储器块阵列提供写入数据的写入选择电路，以及数据保持测试电路，用于将具有对应于逻辑高的电平的写入数据减少到对应于逻辑低加上抵消。

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