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1. 发明申请

WO2023278022A1 SYSTEM AND METHOD FOR PERFORMING RATE ADAPTATION OF CONSTANT BIT RATE (CBR) CLIENT DATA WITH A FIXED NUMBER OF IDLE BLOCKS FOR TRANSMISSION OVER A METRO TRANSPORT NETWORK (MTN) 审中-公开
公开(公告)号：WO2023278022A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/029563
申请日：2022-05-17
申请人： MICROCHIP TECHNOLOGY INC.
发明人： GORSHE, Steven Scott , MOK, Winston
IPC分类号： H04J3/07 , H04J3/16
摘要： A system and method for performing rate adaptation of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of pseudo-Ethernet packets at a source node, assembling a plurality of Generic Mapping Procedure (GMP) frames by mapping a plurality of blocks from a stream of encoded blocks of CBR client data, a plurality of pad blocks, and GMP overhead into consecutive pseudo-Ethernet packets of the plurality of pseudo- Ethernet packets, inserting a fixed number of idle blocks between one or more of the consecutive pseudo-Ethernet packets and inserting an MTN path overhead (POH) frame that is aligned to the plurality of GMP frames to generate a plurality of rate adapted GMP frames for transmission over the MTN to an intermediate node or a sink node.

2. 发明申请

WO2022245385A1 MACHINE LEARNING ASSISTED QUALITY OF SERVICE (QOS) FOR SOLID STATE DRIVES 审中-公开
公开(公告)号：WO2022245385A1
公开(公告)日：2022-11-24
申请号：PCT/US2021/053250
申请日：2021-10-01
申请人： MICROCHIP TECHNOLOGY INC.
发明人： ZUOLO, Lorenzo , MICHELONI, Rino
IPC分类号： G06F3/06 , G06N3/04 , G06N3/08
摘要： A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.

3. 发明申请

WO2022098380A1 REDUNDANT ANGULAR POSITION SENSOR AND ASSOCIATED METHOD OF USE 审中-公开
公开(公告)号：WO2022098380A1
公开(公告)日：2022-05-12
申请号：PCT/US2021/013288
申请日：2021-01-13
申请人： MICROCHIP TECHNOLOGY INC.
发明人： SHAGA, Ganesh
IPC分类号： G01D5/20 , G01D3/08
摘要： A redundant angular position sensor comprising a first angular position sensor including a first excitation coil, a first sensing coil and a second sensing coil and a second angular position sensor. The second angular position sensor including a second excitation coil, a third sensing coil and a fourth sensing coil. Each of the first, second, third and fourth sensing coils comprising a respective clockwise winding portion and a respective counter-clockwise winding portion. The redundant angular position sensor further comprises a rotatable inductive coupling element positioned in overlying relation to the sensing coils and separated from the sensing coils by a gap, wherein the rotatable inductive coupling element comprises four, substantially evenly radially spaced, sector apertures.

4. 发明申请

WO2021141630A1 DAISY-CHAINED SYNCHRONOUS ETHERNET CLOCK RECOVERY 审中-公开
公开(公告)号：WO2021141630A1
公开(公告)日：2021-07-15
申请号：PCT/US2020/041194
申请日：2020-07-08
申请人： MICROCHIP TECHNOLOGY INC.
发明人： JOERGENSEN, Thomas , BRANSCOMB, Brian
IPC分类号： H04J3/06 , H04J3/0688 , H04J3/0697 , H04L49/351 , H04L7/0079
摘要： A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

5. 发明申请

WO2021080639A1 APPARATUS AND METHOD FOR INCORPORATING MULTI-ACTUATOR HARD DISK DRIVES INTO TRADITIONAL RAID ARRAYS 审中-公开
公开(公告)号：WO2021080639A1
公开(公告)日：2021-04-29
申请号：PCT/US2020/021486
申请日：2020-03-06
申请人： MICROCHIP TECHNOLOGY INC.
发明人： CALDWELL, Robert E., Jr.
IPC分类号： G06F3/06 , G11B5/55 , G06F11/10
摘要： A method for operating a storage controller to write to a group of multi-actuator disk drives includes receiving a data stream, performing RAID mapping to a preselected RAID level, organizing the data stream into at least one data stream, creating at least one parity data stream, organizing each data stream and parity data stream into blocks of data, dividing each data stream and each parity data stream into groups of blocks of data assigned to a logical unit representing a drive and an actuator, blocks of data from a data stream and parity stream assigned to a different drive, sequential groups of blocks of data assigned substantially equally to logical units representing actuators in each drive, providing each group of blocks of data to a target port associated with the drive to which it has been assigned, and sending each group of blocks of data from the target port.

6. 发明申请

WO2015200461A1 SEQUENTIAL LINEAR LED DRIVER UTILIZING HEADROOM CONTROL 审中-公开
标题翻译：顺序线性LED驱动器利用HEADROOM控制
公开(公告)号：WO2015200461A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/037381
申请日：2015-06-24
申请人： MICROCHIP TECHNOLOGY INC.
发明人： LYNCH, Scott , CHOY, Benedict
IPC分类号： H05B33/08
CPC分类号： H05B33/083 , H05B33/0845
摘要： A sequential linear light emitting diode (LED) driver utilizing a headroom control technique is disclosed. A headroom control circuit with a micro-tapped segment of LEDs causes one or more of said LEDs to emit light before the direct current voltage is sufficiently high to cause the main LED string(s) to emit light.
摘要翻译：公开了一种使用净空控制技术的顺序线性发光二极管（LED）驱动器。具有LED的微抽头段的裕量控制电路使得一个或多个所述LED在直流电压足够高之前发光，以使主LED串发光。

7. 发明申请

WO2015200454A1 SEQUENTIAL LINEAR LED SYSTEM WITH LOW OUTPUT RIPPLE 审中-公开
标题翻译：具有低输出纹波的顺序线性LED系统
公开(公告)号：WO2015200454A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/037372
申请日：2015-06-24
申请人： MICROCHIP TECHNOLOGY INC.
发明人： LYNCH, Scott
IPC分类号： H05B33/08
CPC分类号： H05B33/0812 , H05B33/0827 , H05B33/083 , H05B33/0845 , Y02B20/348
摘要： A sequential linear light emitting diode (LED) system with a low output ripple is disclosed. In one embodiment, the a sequential linear LED system comprises a bridge rectifier for generating a DC voltage, a diode for receiving the DC voltage, a capacitor coupled to the diode, a current regulator coupled to the capacitor for controlling the charging of the capacitor, and a plurality of segments coupled to the diode, each segment comprising an LED string and current regulator.
摘要翻译：公开了具有低输出纹波的顺序线性发光二极管（LED）系统。在一个实施例中，顺序线性LED系统包括用于产生DC电压的桥式整流器，用于接收DC电压的二极管，耦合到二极管的电容器，耦合到电容器的电流调节器，用于控制电容器的充电，以及耦合到二极管的多个段，每个段包括LED串和电流调节器。

8. 发明申请

WO1997045958A1 CONFIGURABLE INTEGRATED CIRCUIT PINS 审中-公开
标题翻译：可配置集成电路引脚
公开(公告)号：WO1997045958A1
公开(公告)日：1997-12-04
申请号：PCT/US1997006483
申请日：1997-04-12
申请人： MICROCHIP TECHNOLOGY, INC.
发明人： MICROCHIP TECHNOLOGY, INC. , HULL, Richard, L. , ELLISON, Scott
IPC分类号： H03K19/0175
CPC分类号： H03K19/01759
摘要： The invention relates to a configurable IC device pin (14), which may be either a device clock input pin or a digital I/O pin in one embodiment, or a reset pin or a digital I/O pin in another embodiment. Both embodiments use a memory device (16) to store configuration data for the pin. Input/output logic (18) is also used in both embodiments to transfer data to and from the IC pin (14) when configured as a digital I/O pin.
摘要翻译：本发明涉及一种可配置IC器件引脚（14），其可以是一个实施例中的器件时钟输入引脚或数字I / O引脚，或者另一实施例中的复位引脚或数字I / O引脚。两个实施例都使用存储器件（16）来存储引脚的配置数据。当配置为数字I / O引脚时，两个实施例中还使用输入/输出逻辑（18）来将数据传送到IC引脚（14）。

9. 发明申请

WO1993010492A1 SELF-PROGRAMMING MICROCONTROLLER WITH STORED INSTRUCTION TO COMMAND PROGRAM FROM EXTERNAL MEMORY 审中-公开
标题翻译：具有存储指令的自编程微控制器从外部存储器命令程序
公开(公告)号：WO1993010492A1
公开(公告)日：1993-05-27
申请号：PCT/US1992009464
申请日：1992-11-12
申请人： MICROCHIP TECHNOLOGY INC.
发明人： MICROCHIP TECHNOLOGY INC. , CHEN, Chao-Wu , ROSENHAGEN, Kurt , ITALIANO, Greg , MITRA, Sumit
IPC分类号： G06F09/06
CPC分类号： G06F9/24 , G06F9/445
摘要： A microcontroller (10) fabricated on a semiconductor chip is adapted, when operating, to execute programs (17) and instructions and, in response, to generate control signals to selectively control external apparatus. A clock (15) generates timing signals to control the timing of the microcontroller execution and operation. An on-chip program memory (17) has space available for storing a program to be executed by the microcontroller in sequential steps in successive address locations of the program memory. An instruction stored in unerasable memory on the chip initiates self-programming of the program memory with the program to be executed by the microcontroller by enabling a pointer timed by the clock to alternately read addresses containing steps of the program to be executed from off-chip memories and to write same into successive addresses of the on-chip program memory by incrementing the latter addresses with each step to be written therein.
摘要翻译：制造在半导体芯片上的微控制器（10）在操作时适于执行程序（17）和指令，并且作为响应，适于产生控制信号以选择性地控制外部设备。时钟（15）产生定时信号以控制微控制器执行和操作的时序。片上程序存储器（17）具有可用于在程序存储器的连续地址位置中按顺序存储要由微控制器执行的程序的空间。存储在芯片上的不可擦除存储器中的指令通过使由时钟指针定时的指针交替地读取包含要从芯片外执行的程序的步骤的地址，从而启动程序存储器的自编程，并使程序由微控制器执行存储器，并且通过用要在其中写入的每个步骤递增后一个地址，将其写入片上程序存储器的连续地址。

10. 发明申请

WO2023059377A1 EMBEDDED PROCESSOR SUPPORTING FIXED-FUNCTION KERNELS 审中-公开
公开(公告)号：WO2023059377A1
公开(公告)日：2023-04-13
申请号：PCT/US2022/036475
申请日：2022-07-08
申请人： MICROCHIP TECHNOLOGY INC.
发明人： SEVERANCE, Aaron , GREENE, Jonathan W. , VANDERGRIENDT, Joel
IPC分类号： G06F15/78 , G06F15/7867
摘要： A method and apparatus for embedding a microprocessor in a programmable logic device (PLD), where the microprocessor has a logic unit that can operate in two modes. A first mode is a general purpose mode running at least one general purpose process related to the PLD, and a second mode is a fixed function mode emulating a fixed function for use by logic configured into a fabric of the PLD (fabric). A memory unit is coupled to the logic unit and to the fabric, and the fabric is operable for transferring signals with the logic unit in relation to the fixed function.

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