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    • 3. 发明申请
    • SYSTEM AND METHOD FOR CONTROLLING AT LEAST TWO POWER SEMICONDUCTORS CONNECTED IN PARALLEL
    • 用于控制并联连接的最小二功率半导体的系统和方法
    • WO2011067288A1
    • 2011-06-09
    • PCT/EP2010/068637
    • 2010-12-01
    • ABB TECHNOLOGY AGKLAKA, SvenHARTMANN, Samuel
    • KLAKA, SvenHARTMANN, Samuel
    • H03K17/06H03K17/12
    • H03K17/127H02M1/088H02M2001/325H03K17/06
    • The system according to the invention comprises at least two power semiconductor chips (1, 2, 3, 4) being connected in parallel and comprising each a gate terminal for switching the power semiconductor chip (1, 2, 3, 4) in a blocking- state by a first gate voltage and for switching the power semiconductor chip (1, 2, 3, 4) in a conducting- state by a second gate voltage. The system comprises further a control means (16, 57) adapted for applying the first or the second gate voltage to the gate terminals of the at least two power semiconductor chips (1, 2, 3, 4). The control means (16) is adapted for applying a third gate voltage to the gate terminal of the at least one remaining power semiconductor chip (1, 2, 3, 4) when a power semiconductor chip (1, 2, 3, 4) fails, and that the third gate voltage is higher than the second gate voltage.
    • 根据本发明的系统包括并联连接的至少两个功率半导体芯片(1,2,3,4),每个功率半导体芯片包括用于将功率半导体芯片(1,2,3,4)封闭的栅极端子 - 通过第一栅极电压状态,并且用于通过第二栅极电压将导通状态的功率半导体芯片(1,2,3,4)切换。 该系统还包括适于将第一或第二栅极电压施加到至少两个功率半导体芯片(1,2,3,4)的栅极端子的控制装置(16,57)。 控制装置(16)适于在功率半导体芯片(1,2,3,4)的功率半导体芯片(1,2,3,4)上施加第三栅极电压至所述至少一个剩余功率半导体芯片(1,2,3,4)的栅极端子, 并且第三栅极电压高于第二栅极电压。