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1. 发明申请

WO2007087507A3 FIRMWARE SOCKET MODULE FOR FPGA-BASED PIPELINE PROCESSING 审中-公开
标题翻译：用于基于FPGA的管道处理的固件插座模块
公开(公告)号：WO2007087507A3
公开(公告)日：2007-09-13
申请号：PCT/US2007060835
申请日：2007-01-22
申请人： EXEGY INC , UNIV WASHINGTON , CHAMBERLAIN ROGER D , SHANDS E F BERKLEY , BRODIE BENJAMIN C , HENRICHS MICHAEL , WHITE JASON R
发明人： CHAMBERLAIN ROGER D , SHANDS E F BERKLEY , BRODIE BENJAMIN C , HENRICHS MICHAEL , WHITE JASON R
IPC分类号： G06F15/78 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3879
摘要： A firmware socket module is deployed on a reconfigurable logic device, wherein the firmware socket module has a communication path between itself and an entry point into a data processing pipeline, wherein the firmware socket module is configured to provide both commands and target data to the entry point in the data processing pipeline via the same communication path, wherein each command defines a data processing operation that is to be performed by the data processing pipeline, and wherein the target data corresponds to the data upon which the data processing pipeline performs its commanded data processing operation. Preferably, the firmware socket module is configured to provide the commands and target data in a predetermined order that is maintained throughout the data processing pipeline. Also, the firmware socket module may be configured to (1) access an external input descriptor pool buffer that defines the order in which commands and target data are to be provided to the data processing pipeline, and (2) transfer the commands and target data from an external memory to the data processing pipeline in accordance with the identified defined order. Results of the processing by the data processing pipeline are also returned to external memory by the firmware socket module, whereupon those results can be subsequently used by software executing on a computer system.
摘要翻译：固件插座模块部署在可重新配置的逻辑设备上，其中固件插座模块在其与进入数据处理流水线的入口点之间具有通信路径，其中，固件插座模块被配置为向命令提供命令和目标数据通过相同的通信路径指向数据处理流水线，其中每个命令定义要由数据处理流水线执行的数据处理操作，并且其中目标数据对应于数据处理流水线在其上执行其命令数据的数据处理操作。优选地，固件插座模块被配置为按照在整个数据处理流水线中维护的预定顺序提供命令和目标数据。此外，固件插座模块可以被配置为（1）访问外部输入描述符池缓冲器，该外部输入描述符池缓冲器定义要向数据处理流水线提供命令和目标数据的顺序，以及（2）传送命令和目标数据根据所确定的定义顺序从外部存储器传输到数据处理流水线。数据处理流水线的处理结果也由固件插座模块返回到外部存储器，随后可以在计算机系统上执行的软件随后使用这些结果。

2. 发明申请

WO2007121035A3 METHOD AND SYSTEM FOR HIGH THROUGHPUT BLOCKWISE INDEPENDENT ENCRYPTION/DECRYPTION 审中-公开
标题翻译：用于高速插入块独立加密/解码的方法和系统
公开(公告)号：WO2007121035A3
公开(公告)日：2008-09-18
申请号：PCT/US2007064712
申请日：2007-03-22
申请人： EXEGY INC , TAYLOR DAVID E , INDECK RONALD S , WHITE JASON R , CHAMBERLAIN ROGER D
发明人： TAYLOR DAVID E , INDECK RONALD S , WHITE JASON R , CHAMBERLAIN ROGER D
IPC分类号： H04L9/28 , H04K1/00 , H04K1/04 , H04K1/06
CPC分类号： H04L9/0637 , H04L9/0662 , H04L9/14 , H04L2209/125 , H04L2209/24
摘要： An encryption technique is disclosed for encrypting a data segment comprising a plurality of data blocks, wherein the security and throughput of the encryption is enhanced by using blockwise independent bit vectors for reversible combination with the data blocks prior to key encryption. Preferably, the blockwise independent bit vectors are derived from a data tag associated with the data segment. Several embodiments are disclosed for generating these blockwise independent bit vectors. In a preferred embodiment, the data tag comprises a logical block address (LBA) for the data segment. Also disclosed herein is a corresponding decryption technique as well as a corresponding symmetrical encryption/decryption technique.
摘要翻译：公开了一种用于加密包括多个数据块的数据段的加密技术，其中通过在密钥加密之前使用与数据块可逆组合的块独立比特向量来增强加密的安全性和吞吐量。优选地，从与数据段相关联的数据标签导出块独立比特向量。公开了用于产生这些块独立比特向量的几个实施例。在优选实施例中，数据标签包括用于数据段的逻辑块地址（LBA）。这里也公开了相应的解密技术以及对应的对称加密/解密技术。

3. 发明申请

WO2007064685A3 METHOD AND DEVICE FOR HIGH PERFORMANCE REGULAR EXPRESSION PATTERN MATCHING 审中-公开
标题翻译：用于高性能正则表达式匹配的方法和装置
公开(公告)号：WO2007064685A3
公开(公告)日：2008-10-02
申请号：PCT/US2006045653
申请日：2006-11-29
申请人： EXEGY INC , CYTRON RON K , TAYLOR DAVID EDWARD , BRODIE BENJAMIN CURRY
发明人： CYTRON RON K , TAYLOR DAVID EDWARD , BRODIE BENJAMIN CURRY
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , Y10S707/99936
摘要： Disclosed herein is an improved architecture for regular expression pattern matching. Improvements to pattern matching deterministic finite automatons (DFAs) that are described by the inventors include a pipelining strategy that pushes state-dependent feedback to a final pipeline stage to thereby enhance parallelism and throughput, augmented state transitions that track whether a transition is indicative of a pattern match occurring thereby reducing the number of necessary states for the DFA, augmented state transition that track whether a transition is indicative of a restart to the matching process, compression of the DFA's transition table, alphabet encoding for input symbols to equivalence class identifiers, the use of an indirection table to allow for optimized transition table memory, and enhanced scalability to facilitate the ability of the improved DFA to process multiple input symbols per cycle.
摘要翻译：这里公开了用于正则表达式模式匹配的改进的架构。由发明人描述的对模式匹配确定性有限自动机（DFA）的改进包括流水线策略，其将状态相关反馈推送到最终流水线级，从而增强并行度和吞吐量，增强的状态转换，跟踪转移是否指示模式匹配发生，从而减少了DFA的必要状态数量，增强状态转换，跟踪转移是否指示重新启动到匹配过程，DFA转换表的压缩，输入符号的字母编码等价类标识符，使用间接表来允许优化的转换表存储器，以及增强的可扩展性，以便于改进的DFA在每个周期处理多个输入符号的能力。

4. 发明申请

WO2009089467A3 METHOD AND SYSTEM FOR LOW LATENCY BASKET CALCULATION 审中-公开
标题翻译：低年龄篮子计算方法与系统
公开(公告)号：WO2009089467A3
公开(公告)日：2009-12-30
申请号：PCT/US2009030623
申请日：2009-01-09
申请人： EXEGY INC , TAYLOR DAVID E , SINGLA NAVEEN , BRODIE BENJAMIN C , MCVICAR NATHANIEL S , THIEL JUSTIN R , INDECK RONALD S
发明人： TAYLOR DAVID E , SINGLA NAVEEN , BRODIE BENJAMIN C , MCVICAR NATHANIEL S , THIEL JUSTIN R , INDECK RONALD S
IPC分类号： G06Q40/00
CPC分类号： G06Q40/00 , G06Q40/06
摘要： A basket calculation engine is deployed to receive a stream of data and accelerate the computation of basket values based on that data. In a preferred embodiment, the basket calculation engine is used to process financial market data to compute the net asset values (NAVs) of financial instrument baskets. The basket calculation engine can be deployed on a coprocessor and can also be realized via a pipeline, the pipeline preferably comprising a basket association lookup module and a basket value updating module. The coprocessor is preferably a reconfigurable logic device such as a field programmable gate array (FPGA).
摘要翻译：部署篮子计算引擎以接收数据流，并基于该数据加速计算篮值。在优选实施例中，篮子计算引擎用于处理金融市场数据以计算金融工具篮子的净资产值（NAV）。篮子计算引擎可以部署在协处理器上，并且也可以通过管道实现，管线优选地包括篮关联查找模块和篮值更新模块。协处理器优选地是诸如现场可编程门阵列（FPGA）的可重新配置的逻辑器件。

5. 发明申请

WO2008063974A3 METHOD AND SYSTEM FOR HIGH PERFORMANCE INTEGRATION, PROCESSING AND SEARCHING OF STRUCTURED AND UNSTRUCTURED DATA USING COPROCESSORS 审中-公开
标题翻译：使用协处理器的结构化和非结构化数据的高性能集成，处理和搜索的方法和系统
公开(公告)号：WO2008063974A3
公开(公告)日：2008-11-20
申请号：PCT/US2007084466
申请日：2007-11-12
申请人： EXEGY INC , INDECK RONALD S , INDECK DAVID MARK
发明人： INDECK RONALD S , INDECK DAVID MARK
IPC分类号： G06F17/30
CPC分类号： G06F17/30943
摘要： Disclosed herein is a method and system for integrating an enterprise's structured and unstructured data to provide users and enterprise applications with efficient and intelligent access to that data. Queries can be directed toward both an enterprise's structured and unstructured data using standardized database query formats such as SQL commands. A coprocessor can be used to hardware-accelerate data processing tasks (such as full-text searching) on unstructured data as necessary to handle a query. Furthermore, traditional relational database techniques can be used to access structured data stored by a relational database to determine which portions of the enterprise's unstructured data should be delivered to the coprocessor for hardware-accelerated data processing.
摘要翻译：本文公开了一种用于集成企业的结构化和非结构化数据以向用户和企业应用程序提供对该数据的高效和智能访问的方法和系统。查询可以使用标准化的数据库查询格式（如SQL命令）针对企业的结构化和非结构化数据。可以使用协处理器对处理查询所需的非结构化数据进行硬件加速数据处理任务（如全文搜索）。此外，传统的关系数据库技术可以用于访问由关系数据库存储的结构化数据，以确定企业的非结构化数据的哪些部分应该传送到协处理器进行硬件加速数据处理。

6. 发明申请

WO2008063973A2 METHOD AND SYSTEM FOR HIGH PERFORMANCE DATA METATAGGING AND DATA INDEXING USING COPROCESSORS 审中-公开
标题翻译：用于高性能数据分类和使用协处理器的数据索引的方法和系统
公开(公告)号：WO2008063973A2
公开(公告)日：2008-05-29
申请号：PCT/US2007084464
申请日：2007-11-12
申请人： EXEGY INC , INDECK RONALD S , SINGLA NAVEEN , TAYLOR DAVID E
发明人： INDECK RONALD S , SINGLA NAVEEN , TAYLOR DAVID E
IPC分类号： G06F17/30
CPC分类号： G06F17/30943
摘要： Disclosed herein is a method and system for hardware-accelerating the generation of metadata for a data stream using a coprocessor. Using these techniques, data can be richly indexed, classified, and clustered at high speeds. Reconfigurable logic such a field programmable gate arrays (FPGAs) can be used by the coprocessor for this hardware acceleration. Techniques such as exact matching, approximate matching, and regular expression pattern matching can be employed by the coprocessor to generate desired metadata for the data stream.
摘要翻译：这里公开了一种用于硬件加速使用协处理器为数据流生成元数据的方法和系统。使用这些技术，数据可以高速索引，分类和集群。协调处理器可以使用这种现场可编程门阵列（FPGA）的可重构逻辑来进行该硬件加速。协处理器可以采用诸如精确匹配，近似匹配和正则表达式模式匹配的技术来生成用于数据流的期望的元数据。

7. 发明申请

WO2007130818A3 METHOD AND APPARATUS FOR APPROXIMATE PATTERN MATCHING 审中-公开
标题翻译：用于大致图案匹配的方法和装置
公开(公告)号：WO2007130818A3
公开(公告)日：2008-02-28
申请号：PCT/US2007067319
申请日：2007-04-24
申请人： EXEGY INC , TAYLOR DAVID EDWARD
发明人： TAYLOR DAVID EDWARD
IPC分类号： H04L29/06
CPC分类号： H04L63/0245 , G06F19/22 , H04L63/1416 , H04L63/145
摘要： A system and method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error, which includes filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms, detecting a plurality of potential pattern piece matches, identifying a plurality of potentially matching patterns, reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns with a reduction stage, providing associated data and the reduced set of potentially matching patterns, each having an associated allowable error, to a verification stage, and verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations and associated allowable errors with the verification stage.
摘要翻译：一种用于检查数据流的系统和方法，用于匹配具有预定可允许误差的一个或多个模式的数据段，其包括用多个并行过滤机构对符号组合的多个模式进行数据流的过滤，检测多个潜在图案片匹配，识别多个潜在匹配模式，将所识别的多个潜在匹配模式减少到具有减少级的一组潜在匹配模式，提供相关联的数据和所述缩减的潜在匹配模式集合，每组具有相关联的允许错误，到验证阶段，以及验证来自多个符号组合模式的数据流中的模式匹配的存在以及与验证阶段相关联的允许错误。

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